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bdk: max77620: reduce max DRAM VDDIO/Q
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
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418f029d11
commit
18f3a1b70c
2 changed files with 4 additions and 4 deletions
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@ -75,7 +75,7 @@ typedef struct _max77620_regulator_t
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static const max77620_regulator_t _pmic_regulators[] = {
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static const max77620_regulator_t _pmic_regulators[] = {
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{ "sd0", 12500, 600000, 625000, 1400000, REGULATOR_SD, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, {{ MAX77620_REG_FPS_SD0, 1, 7, 1 }} },
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{ "sd0", 12500, 600000, 625000, 1400000, REGULATOR_SD, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, {{ MAX77620_REG_FPS_SD0, 1, 7, 1 }} },
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{ "sd1", 12500, 600000, 1125000, 1250000, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} },
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{ "sd1", 12500, 600000, 1125000, 1175000, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} },
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{ "sd2", 12500, 600000, 1325000, 1350000, REGULATOR_SD, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD2, 1, 5, 2 }} },
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{ "sd2", 12500, 600000, 1325000, 1350000, REGULATOR_SD, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD2, 1, 5, 2 }} },
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{ "sd3", 12500, 600000, 1800000, 1800000, REGULATOR_SD, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD3, 0, 3, 3 }} },
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{ "sd3", 12500, 600000, 1800000, 1800000, REGULATOR_SD, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD3, 0, 3, 3 }} },
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{ "ldo0", 25000, 800000, 1200000, 1200000, REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
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{ "ldo0", 25000, 800000, 1200000, 1200000, REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
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@ -123,7 +123,7 @@ static u8 _max7762x_get_i2c_address(u32 id)
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case REGULATOR_BC1:
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case REGULATOR_BC1:
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{
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{
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u8 reg_addr = _max77812_get_address();
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u8 reg_addr = _max77812_get_address();
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if (id == REGULATOR_RAM1 && reg_addr == MAX77812_PHASE31_CPU_I2C_ADDR)
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if (id == REGULATOR_RAM0 && reg_addr == MAX77812_PHASE31_CPU_I2C_ADDR)
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reg_addr = 0;
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reg_addr = 0;
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return reg_addr;
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return reg_addr;
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}
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}
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@ -69,9 +69,9 @@
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#define REGULATOR_CPU0 13 // T210 CPU.
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#define REGULATOR_CPU0 13 // T210 CPU.
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#define REGULATOR_GPU0 14 // T210 CPU.
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#define REGULATOR_GPU0 14 // T210 CPU.
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#define REGULATOR_CPU1 15 // T210B01 CPU.
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#define REGULATOR_CPU1 15 // T210B01 CPU.
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#define REGULATOR_RAM1 16 // T210B01 RAM for PHASE211.
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#define REGULATOR_RAM0 16 // T210B01 RAM for PHASE211.
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//#define REGULATOR_GPU1 17 // T210B01 CPU.
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//#define REGULATOR_GPU1 17 // T210B01 CPU.
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#define REGULATOR_MAX REGULATOR_RAM1
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#define REGULATOR_MAX REGULATOR_RAM0
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_GPU_I2C_ADDR 0x1C
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#define MAX77621_GPU_I2C_ADDR 0x1C
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