mirrors/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate.git synced 2024-11-26 11:42:09 +00:00
Code Issues Releases Activity

minerva: update copyright years

Browse source
This commit is contained in:
CTCaer 2022-01-20 13:22:39 +02:00
parent 192a936a31
commit 20c4d6dba6
2 changed files with 2 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
modules/hekate_libsys_minerva/mtc.h
View file

@ -2,7 +2,7 @@
* Minerva Training Cell * Minerva Training Cell
* DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4. * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4.
* *
* Copyright (c) 2018 CTCaer <ctcaer@gmail.com> * Copyright (c) 2018-2022 CTCaer <ctcaer@gmail.com>
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

2
modules/hekate_libsys_minerva/sys_sdrammtc.c
View file

@ -2,7 +2,7 @@
* Minerva Training Cell * Minerva Training Cell
* DRAM Training for Tegra X1 SoC. Supports LPDDR4. * DRAM Training for Tegra X1 SoC. Supports LPDDR4.
* *
* Copyright (c) 2018-2021 CTCaer <ctcaer@gmail.com> * Copyright (c) 2018-2022 CTCaer <ctcaer@gmail.com>
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,