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bdk: max77812: uncomment RAM regulator
This commit is contained in:
parent
c52c11e7bc
commit
2aa251c44f
3 changed files with 24 additions and 24 deletions
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@ -318,7 +318,7 @@
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#define MAX77620_REG_CID2 0x5A
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#define MAX77620_REG_CID2 0x5A
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#define MAX77620_REG_CID3 0x5B
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#define MAX77620_REG_CID3 0x5B
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#define MAX77620_REG_CID4 0x5C // OTP version.
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#define MAX77620_REG_CID4 0x5C // OTP version.
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#define MAX77620_REG_CID5 0x5D
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#define MAX77620_REG_CID5 0x5D // ES version.
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#define MAX77620_CID_DIDO_MASK 0xF
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#define MAX77620_CID_DIDO_MASK 0xF
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#define MAX77620_CID_DIDO_SHIFT 0
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#define MAX77620_CID_DIDO_SHIFT 0
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#define MAX77620_CID_DIDM_MASK 0xF0
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#define MAX77620_CID_DIDM_MASK 0xF0
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@ -88,11 +88,11 @@ static const max77620_regulator_t _pmic_regulators[] = {
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{ "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
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{ "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
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{ "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
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{ "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
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{ "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
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{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
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{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
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{ "max77812_RAM", 5000, 250000, 600000, 650000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
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//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
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//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
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//{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
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};
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};
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static u8 _max77812_get_address()
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static u8 _max77812_get_address()
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@ -175,20 +175,20 @@ int max77620_regulator_config_fps(u32 id)
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return 1;
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return 1;
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}
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}
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int max7762x_regulator_set_voltage(u32 id, u32 mv)
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int max7762x_regulator_set_voltage(u32 id, u32 uv)
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{
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{
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if (id > REGULATOR_MAX)
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if (id > REGULATOR_MAX)
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return 0;
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return 0;
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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const max77620_regulator_t *reg = &_pmic_regulators[id];
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if (mv < reg->uv_min || mv > reg->uv_max)
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if (uv < reg->uv_min || uv > reg->uv_max)
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return 0;
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return 0;
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u8 addr = _max7762x_get_i2c_address(id);
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u8 addr = _max7762x_get_i2c_address(id);
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// Calculate voltage multiplier.
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// Calculate voltage multiplier.
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u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
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u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
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u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
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u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
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val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
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val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
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@ -299,13 +299,13 @@ void max77621_config_default(u32 id, bool por)
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max7762x_regulator_enable(id, false);
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max7762x_regulator_enable(id, false);
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// Configure to default.
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// Configure to default.
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por);
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i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_por);
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por);
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i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_por);
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}
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}
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else
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else
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{
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{
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos);
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i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_hos);
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i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos);
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i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_hos);
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}
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}
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}
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}
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@ -66,22 +66,22 @@
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#define REGULATOR_LDO6 10
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#define REGULATOR_LDO6 10
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#define REGULATOR_LDO7 11
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#define REGULATOR_LDO7 11
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#define REGULATOR_LDO8 12
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#define REGULATOR_LDO8 12
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#define REGULATOR_CPU0 13
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#define REGULATOR_CPU0 13 // T210 CPU.
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#define REGULATOR_GPU0 14
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#define REGULATOR_GPU0 14 // T210 CPU.
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#define REGULATOR_CPU1 15
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#define REGULATOR_CPU1 15 // T210B01 CPU.
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//#define REGULATOR_GPU1 16
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#define REGULATOR_RAM1 16 // T210B01 RAM for PHASE211.
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//#define REGULATOR_GPU1 17
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//#define REGULATOR_GPU1 17 // T210B01 CPU.
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#define REGULATOR_MAX 15
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#define REGULATOR_MAX REGULATOR_RAM1
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_GPU_I2C_ADDR 0x1C
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#define MAX77621_GPU_I2C_ADDR 0x1C
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#define MAX77621_VOUT_REG 0x00
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#define MAX77621_REG_VOUT 0x00
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#define MAX77621_VOUT_DVS_REG 0x01
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#define MAX77621_REG_VOUT_DVS 0x01
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#define MAX77621_CONTROL1_REG 0x02
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#define MAX77621_REG_CONTROL1 0x02
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#define MAX77621_CONTROL2_REG 0x03
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#define MAX77621_REG_CONTROL2 0x03
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#define MAX77621_CHIPID1_REG 0x04
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#define MAX77621_REG_CHIPID1 0x04
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#define MAX77621_CHIPID2_REG 0x05
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#define MAX77621_REG_CHIPID2 0x05
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/* MAX77621_VOUT_DVC_DVS */
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/* MAX77621_VOUT_DVC_DVS */
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#define MAX77621_DVC_DVS_VOLT_MASK 0x7F
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#define MAX77621_DVC_DVS_VOLT_MASK 0x7F
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@ -145,7 +145,7 @@
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int max77620_regulator_get_status(u32 id);
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int max77620_regulator_get_status(u32 id);
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int max77620_regulator_config_fps(u32 id);
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int max77620_regulator_config_fps(u32 id);
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int max7762x_regulator_set_voltage(u32 id, u32 mv);
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int max7762x_regulator_set_voltage(u32 id, u32 uv);
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int max7762x_regulator_enable(u32 id, bool enable);
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int max7762x_regulator_enable(u32 id, bool enable);
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void max77620_config_gpio(u32 id, bool enable);
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void max77620_config_gpio(u32 id, bool enable);
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void max77620_config_default();
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void max77620_config_default();
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