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bdk: hwinit: move sd2 to hw init
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init. Also there's not need to power it down first so configure it in one go.
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2 changed files with 12 additions and 12 deletions
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@ -373,17 +373,6 @@ void display_init()
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// Get Chip ID.
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// Get Chip ID.
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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// T210B01: Power on SD2 regulator for supplying LDO0.
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if (!tegra_t210)
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{
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// Set SD2 regulator voltage.
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max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000);
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// Set slew rate and enable SD2 regulator.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
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max7762x_regulator_enable(REGULATOR_SD2, true);
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}
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// Enable LCD DVDD.
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// Enable LCD DVDD.
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max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000);
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max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000);
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max7762x_regulator_enable(REGULATOR_LDO0, true);
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max7762x_regulator_enable(REGULATOR_LDO0, true);
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@ -333,8 +333,19 @@ static void _config_regulators(bool tegra_t210)
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max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG);
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max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG);
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max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG);
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max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG);
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}
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}
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else // Tegra X1+ set vdd_core voltage to 1.05V.
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else
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{
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// Tegra X1+ set vdd_core voltage to 1.05V.
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000);
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000);
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// Power on SD2 regulator for supplying LDO0/1/8.
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max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000);
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// Set slew rate and enable SD2 regulator.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) |
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(MAX77620_POWER_MODE_NORMAL << MAX77620_SD_POWER_MODE_SHIFT) |
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MAX77620_SD_CFG1_FSRADE_SD_ENABLE);
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}
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}
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}
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void hw_init()
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void hw_init()
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