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Code Issues Releases Activity

bdk: smmu: powergate ccplex after enabling smmu

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CTCaer 2024-03-13 01:44:58 +02:00
parent fb31cb2926
commit 3a4fa12f42
4 changed files with 19 additions and 39 deletions
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40
bdk/mem/smmu.c
View file

@ -23,27 +23,18 @@
#include <soc/t210.h> #include <soc/t210.h>
#include <mem/mc_t210.h> #include <mem/mc_t210.h>
#include <mem/smmu.h> #include <mem/smmu.h>
#include <utils/aarch64_util.h>
bool smmu_used = false;
u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR; u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1; // Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
u8 smmu_payload[] __attribute__((aligned(16))) = { u8 smmu_payload[] __attribute__((aligned(16))) = {
0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010 0xC1, 0x00, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1 0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1] 0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS 0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH 0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop 0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0 0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1]
0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000
0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0
0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
0x00, 0x00, 0x00, 0x00, // 0x2C:
0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
0x00, 0x00, 0x00, 0x00 // 0x34:
}; };
void *page_alloc(u32 num) void *page_alloc(u32 num)
@ -76,7 +67,7 @@ void smmu_flush_all()
smmu_flush_regs(); smmu_flush_regs();
} }
void smmu_init(u32 secmon_base) void smmu_init()
{ {
MC(MC_SMMU_PTB_ASID) = 0; MC(MC_SMMU_PTB_ASID) = 0;
MC(MC_SMMU_PTB_DATA) = 0; MC(MC_SMMU_PTB_DATA) = 0;
@ -84,31 +75,22 @@ void smmu_init(u32 secmon_base)
MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F; MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
MC(MC_SMMU_PTC_FLUSH) = 0; MC(MC_SMMU_PTC_FLUSH) = 0;
MC(MC_SMMU_TLB_FLUSH) = 0; MC(MC_SMMU_TLB_FLUSH) = 0;
// Set the secmon address
*(u32 *)(smmu_payload + 0x30) = secmon_base;
} }
void smmu_enable() void smmu_enable()
{ {
if (smmu_used) static bool enabled = false;
if (enabled)
return; return;
ccplex_boot_cpu0((u32)smmu_payload, true); ccplex_boot_cpu0((u32)smmu_payload, false);
smmu_used = true; msleep(100);
msleep(150); ccplex_powergate_cpu0();
smmu_flush_all(); smmu_flush_all();
}
bool smmu_is_used() enabled = true;
{
return smmu_used;
}
void smmu_exit()
{
*(u32 *)(smmu_payload + 0x14) = _NOP();
} }
u32 *smmu_init_domain4(u32 dev_base, u32 asid) u32 *smmu_init_domain4(u32 dev_base, u32 asid)

5
bdk/mem/smmu.h
View file

@ -1,5 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2024 CTCaer
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -72,10 +73,8 @@ void *page_alloc(u32 num);
u32 *smmu_alloc_pdir(); u32 *smmu_alloc_pdir();
void smmu_flush_regs(); void smmu_flush_regs();
void smmu_flush_all(); void smmu_flush_all();
void smmu_init(u32 secmon_base); void smmu_init();
void smmu_enable(); void smmu_enable();
bool smmu_is_used();
void smmu_exit();
u32 *smmu_init_domain4(u32 dev_base, u32 asid); u32 *smmu_init_domain4(u32 dev_base, u32 asid);
u32 *smmu_get_pte(u32 *pdir, u32 iova); u32 *smmu_get_pte(u32 *pdir, u32 iova);
void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr); void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);

8
bdk/sec/tsec.c
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2023 CTCaer * Copyright (c) 2018-2024 CTCaer
* Copyright (c) 2018 balika011 * Copyright (c) 2018 balika011
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
@ -146,9 +146,9 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
{ {
// Init SMMU translation for TSEC. // Init SMMU translation for TSEC.
pdir = smmu_init_for_tsec(); pdir = smmu_init_for_tsec();
smmu_init(tsec_ctxt->secmon_base); smmu_init();
// Enable SMMU
if (!smmu_is_used()) // Enable SMMU.
smmu_enable(); smmu_enable();
// Clock reset controller. // Clock reset controller.

3
bdk/sec/tsec.h
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2018 naehrwert * Copyright (c) 2018 naehrwert
* Copyright (c) 2018-2021 CTCaer * Copyright (c) 2018-2024 CTCaer
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
@ -35,7 +35,6 @@ typedef struct _tsec_ctxt_t
u32 type; u32 type;
void *pkg1; void *pkg1;
u32 pkg11_off; u32 pkg11_off;
u32 secmon_base;
} tsec_ctxt_t; } tsec_ctxt_t;
int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt); int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt);