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mtc: Clear init magic on chainload

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Fixes a hang caused when rebooting 2 payload from L4T with old hekate in vendor partition.

L4T does not overwrite the nyx storage where the Minerva configuration is stored.
This makes new Minerva parse the wrong tables from old hekate and eventually hang the RAM, which causes an exception on BPMP.
This commit is contained in:
CTCaer 2020-01-14 23:41:15 +02:00
parent 9263e2192f
commit 4d53f21387
2 changed files with 2 additions and 0 deletions
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1
bootloader/soc/hw_init.c
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@ -317,6 +317,7 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
bpmp_mmu_disable(); bpmp_mmu_disable();
bpmp_clk_rate_set(BPMP_CLK_NORMAL); bpmp_clk_rate_set(BPMP_CLK_NORMAL);
minerva_change_freq(FREQ_204); minerva_change_freq(FREQ_204);
nyx_str->mtc_cfg.init_done = 0;
// Re-enable clocks to Audio Processing Engine as a workaround to hanging. // Re-enable clocks to Audio Processing Engine as a workaround to hanging.
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock. CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.

1
nyx/nyx_gui/soc/hw_init.c
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@ -45,6 +45,7 @@ void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
// Flush/disable MMU cache and set DRAM clock to 204MHz. // Flush/disable MMU cache and set DRAM clock to 204MHz.
bpmp_mmu_disable(); bpmp_mmu_disable();
minerva_change_freq(FREQ_204); minerva_change_freq(FREQ_204);
nyx_str->mtc_cfg.init_done = 0;
// Re-enable clocks to Audio Processing Engine as a workaround to hanging. // Re-enable clocks to Audio Processing Engine as a workaround to hanging.
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock. CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.