mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-26 11:42:09 +00:00
Name more hardcoded regs/vals
This commit is contained in:
Kostas Missos
parent
cfef8b4f72
commit
4eb5b5f91b
13 changed files with 185 additions and 95 deletions
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@ -81,7 +81,7 @@ void display_init()
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gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Backlight Enable enable.
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// Config display interface and display.
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MIPI_CAL(0x60) = 0;
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MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
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exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
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@ -94,11 +94,11 @@ void display_init()
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usleep(60000);
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x337;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x406;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x406; // MIPI_DCS_GET_DISPLAY_ID
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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@ -111,12 +111,12 @@ void display_init()
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1105;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(180000);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2905;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; // MIPI_DCS_SET_DISPLAY_ON
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(20000);
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@ -187,7 +187,7 @@ void display_end()
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display_backlight_brightness(0, 1000);
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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@ -200,7 +200,7 @@ void display_end()
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1005;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(50000);
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@ -342,9 +342,10 @@
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#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
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#define DSI_PAD_CONTROL_4 0x52
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#define DSI_INIT_SEQ_DATA_15 0x5F
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#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
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/*! Display backlight related PWM registers. */
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#define PWM_CONTROLLER_PWM_CSR 0x00
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@ -287,12 +287,12 @@ static const cfg_op_t _display_config_7[10] = {
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//MIPI CAL config.
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static const cfg_op_t _display_config_8[6] = {
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{0x18, 0},
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{2, 0xF3F10000},
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{0x16, 0},
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{0x18, 0},
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{0x18, 0x10010},
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{0x17, 0x300}
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{0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
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{0x02, 0xF3F10000}, // MIPI_CAL_CIL_MIPI_CAL_STATUS
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{0x16, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG0
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{0x18, 0}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
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{0x18, 0x10010}, // MIPI_CAL_MIPI_BIAS_PAD_CFG2
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{0x17, 0x300} // MIPI_CAL_MIPI_BIAS_PAD_CFG1
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};
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//DSI config.
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@ -305,22 +305,22 @@ static const cfg_op_t _display_config_9[4] = {
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//MIPI CAL config.
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static const cfg_op_t _display_config_10[16] = {
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{0xE, 0x200200},
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{0xF, 0x200200},
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{0x19, 0x200002},
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{0x1A, 0x200002},
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{5, 0},
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{6, 0},
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{7, 0},
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{8, 0},
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{9, 0},
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{0xA, 0},
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{0x10, 0},
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{0x11, 0},
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{0x1A, 0},
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{0x1C, 0},
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{0x1D, 0},
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{0, 0x2A000001}
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{0x0E, 0x200200}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
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{0x0F, 0x200200}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG
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{0x19, 0x200002}, // MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2
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{0x1A, 0x200002}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
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{0x05, 0}, // MIPI_CAL_CILA_MIPI_CAL_CONFIG
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{0x06, 0}, // MIPI_CAL_CILB_MIPI_CAL_CONFIG
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{0x07, 0}, // MIPI_CAL_CILC_MIPI_CAL_CONFIG
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{0x08, 0}, // MIPI_CAL_CILD_MIPI_CAL_CONFIG
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{0x09, 0}, // MIPI_CAL_CILE_MIPI_CAL_CONFIG
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{0x0A, 0}, // MIPI_CAL_CILF_MIPI_CAL_CONFIG
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{0x10, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG
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{0x11, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG
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{0x1A, 0}, // MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2
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{0x1C, 0}, // MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2
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{0x1D, 0}, // MIPI_CAL_DSID_MIPI_CAL_CONFIG_2
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{0, 0x2A000001} // MIPI_CAL_DSIA_MIPI_CAL_CONFIG
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};
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//Display A config.
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@ -212,10 +212,10 @@ void panic(u32 val)
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// Set panic code.
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PMC(APBDEV_PMC_SCRATCH200) = val;
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//PMC(APBDEV_PMC_CRYPTO_OP) = 1; // Disable SE.
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TMR(0x18C) = 0xC45A;
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TMR(0x80) = 0xC0000000;
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TMR(0x180) = 0x8019;
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TMR(0x188) = 1;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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while (1)
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;
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}
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@ -238,7 +238,7 @@ void reboot_rcm()
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#endif //MENU_LOGO_ENABLE
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display_end();
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PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm.
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PMC(0) |= 0x10;
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PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
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while (true)
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usleep(1);
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}
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@ -280,7 +280,7 @@ void config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4;
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000;
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TMR(0x14) = 0x45F;
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TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071;
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE;
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | 0x400000;
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@ -338,16 +338,16 @@ void mbist_workaround()
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
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usleep(2);
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I2S(0x0A0) |= 0x400;
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I2S(0x088) &= 0xFFFFFFFE;
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I2S(0x1A0) |= 0x400;
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I2S(0x188) &= 0xFFFFFFFE;
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I2S(0x2A0) |= 0x400;
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I2S(0x288) &= 0xFFFFFFFE;
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I2S(0x3A0) |= 0x400;
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I2S(0x388) &= 0xFFFFFFFE;
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I2S(0x4A0) |= 0x400;
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I2S(0x488) &= 0xFFFFFFFE;
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I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S2_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S3_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE;
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DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4;
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VIC(0x8C) = 0xFFFFFFFF;
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usleep(2);
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@ -377,20 +377,30 @@ void mbist_workaround()
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void config_se_brom()
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{
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// Bootrom part we skipped.
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u32 sbk[4] = { FUSE(0x1A4), FUSE(0x1A8), FUSE(0x1AC), FUSE(0x1B0) };
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u32 sbk[4] = {
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FUSE(FUSE_PRIVATE_KEY0),
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FUSE(FUSE_PRIVATE_KEY1),
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FUSE(FUSE_PRIVATE_KEY2),
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FUSE(FUSE_PRIVATE_KEY3)
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};
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// Set SBK to slot 14.
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se_aes_key_set(14, sbk, 0x10);
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// Lock SBK from being read.
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SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 14 * 4) = 0x7E;
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// This memset needs to happen here, else TZRAM will behave weirdly later on.
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memset((void *)0x7C010000, 0, 0x10000);
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memset((void *)TZRAM_BASE, 0, 0x10000);
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PMC(APBDEV_PMC_CRYPTO_OP) = 0;
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SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
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// Lock SSK (although it's not set and unused anyways).
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SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 15 * 4) = 0x7E;
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// Clear the boot reason to avoid problems later
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PMC(APBDEV_PMC_SCRATCH200) = 0x0;
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PMC(APBDEV_PMC_RST_STATUS) = 0x0;
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = 0x1C00;
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) |= (7 << 10);
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}
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void config_hw()
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@ -456,13 +466,13 @@ void config_hw()
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void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
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{
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// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= 0x400; // Enable AHUB clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= 0x40; // Enable APE clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 << 6); // Enable APE clock.
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if (extra_reconfig)
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{
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msleep(10);
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PMC(APBDEV_PMC_PWR_DET_VAL) |= (1 << 12);
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PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
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clock_disable_cl_dvfs();
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@ -499,7 +509,7 @@ void print_fuseinfo()
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burntFuses++;
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}
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gfx_printf(&gfx_con, "\nSKU: %X - ", FUSE(0x110));
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gfx_printf(&gfx_con, "\nSKU: %X - ", FUSE(FUSE_SKU_INFO));
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switch (fuse_read_odm(4) & 3)
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{
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case 0:
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@ -512,7 +522,8 @@ void print_fuseinfo()
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gfx_printf(&gfx_con, "Sdram ID: %d\n", (fuse_read_odm(4) >> 3) & 0x1F);
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gfx_printf(&gfx_con, "Burnt fuses: %d\n", burntFuses);
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gfx_printf(&gfx_con, "Secure key: %08X%08X%08X%08X\n\n\n",
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byte_swap_32(FUSE(0x1A4)), byte_swap_32(FUSE(0x1A8)), byte_swap_32(FUSE(0x1AC)), byte_swap_32(FUSE(0x1B0)));
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byte_swap_32(FUSE(FUSE_PRIVATE_KEY0)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY1)),
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byte_swap_32(FUSE(FUSE_PRIVATE_KEY2)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY3)));
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gfx_printf(&gfx_con, "%k(Unlocked) fuse cache:\n\n%k", 0xFF00DDFF, 0xFFCCCCCC);
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gfx_hexdump(&gfx_con, 0x7000F900, (u8 *)0x7000F900, 0x2FC);
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@ -107,6 +107,7 @@ void mc_config_carveout_finalize()
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void mc_enable_ahb_redirect()
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{
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// Enable ARC_CLK_OVR_ON.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
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//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
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MC(MC_IRAM_BOM) = 0x40000000;
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@ -119,7 +120,8 @@ void mc_disable_ahb_redirect()
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MC(MC_IRAM_TOM) = 0;
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// Disable IRAM_CFG_WRITE_ACCESS (sticky).
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//MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1;
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CLOCK(0x3A4) &= 0xFFF7FFFF;
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// Disable ARC_CLK_OVR_ON.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF;
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}
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void mc_enable()
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@ -19,6 +19,8 @@
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#include "../utils/util.h"
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#include "../storage/sdmmc.h"
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/* clock_t: reset, enable, source, index, clk_src, clk_div */
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static const clock_t _clock_uart[] = {
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/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 },
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/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 },
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@ -28,28 +30,50 @@ static const clock_t _clock_uart[] = {
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};
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static const clock_t _clock_i2c[] = {
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
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/* I2C2 */ { 0 },
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/* I2C3 */ { 0 },
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/* I2C4 */ { 0 },
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
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/* I2C2 */ { 0 },
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/* I2C3 */ { 0 },
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/* I2C4 */ { 0 },
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
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/* I2C6 */ { 0 }
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};
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static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0 };
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static clock_t _clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 };
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static clock_t _clock_se = {
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CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, 0x1F, 0, 0
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};
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static clock_t _clock_unk2 = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, 0x1E, 0, 0
|
||||
};
|
||||
|
||||
static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 };
|
||||
static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 };
|
||||
static clock_t _clock_sor_safe = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 };
|
||||
static clock_t _clock_sor0 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_RST_SOURCE, 0x16, 0, 0 };
|
||||
static clock_t _clock_sor1 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 };
|
||||
static clock_t _clock_kfuse = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_RST_SOURCE, 8, 0, 0 };
|
||||
static clock_t _clock_host1x = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3
|
||||
};
|
||||
static clock_t _clock_tsec = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2
|
||||
};
|
||||
static clock_t _clock_sor_safe = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, 0x1E, 0, 0
|
||||
};
|
||||
static clock_t _clock_sor0 = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE, 0x16, 0, 0
|
||||
};
|
||||
static clock_t _clock_sor1 = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2
|
||||
};
|
||||
static clock_t _clock_kfuse = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, 8, 0, 0
|
||||
};
|
||||
|
||||
static clock_t _clock_cl_dvfs = { CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_RST_CONTROLLER_RST_SOURCE, 0x1B, 0, 0 };
|
||||
static clock_t _clock_coresight = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4};
|
||||
static clock_t _clock_cl_dvfs = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, 0x1B, 0, 0
|
||||
};
|
||||
static clock_t _clock_coresight = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4
|
||||
};
|
||||
|
||||
static clock_t _clock_pwm = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4};
|
||||
static clock_t _clock_pwm = {
|
||||
CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 0x11, 6, 4
|
||||
};
|
||||
|
||||
void clock_enable(const clock_t *clk)
|
||||
{
|
||||
|
|
@ -157,11 +181,11 @@ void clock_disable_sor1()
|
|||
void clock_enable_kfuse()
|
||||
{
|
||||
//clock_enable(&_clock_kfuse);
|
||||
CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100;
|
||||
CLOCK(0x14) &= 0xFFFFFEFF;
|
||||
CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100;
|
||||
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
|
||||
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
|
||||
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
|
||||
usleep(10);
|
||||
CLOCK(0x8) &= 0xFFFFFEFF;
|
||||
CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
|
||||
usleep(20);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -116,6 +116,8 @@
|
|||
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
|
||||
#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
|
||||
|
||||
#define CLK_NO_SOURCE 0x0
|
||||
|
||||
/*! Generic clock descriptor. */
|
||||
typedef struct _clock_t
|
||||
{
|
||||
|
|
|
|||
|
|
@ -30,10 +30,12 @@ void _cluster_enable_power()
|
|||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
|
||||
|
||||
// Enable cores power.
|
||||
// 1-3.x: MAX77621_NFSR_ENABLE.
|
||||
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
|
||||
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); // 1-3.x: MAX77621_NFSR_ENABLE
|
||||
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE);
|
||||
// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
|
||||
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
|
||||
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL); // 1-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL
|
||||
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
|
||||
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37);
|
||||
i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37);
|
||||
}
|
||||
|
|
@ -112,7 +114,7 @@ void cluster_boot_cpu0(u32 entry)
|
|||
while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
|
||||
;
|
||||
|
||||
EXCP_VEC(0x100) = 0;
|
||||
EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0;
|
||||
|
||||
// Set reset vector.
|
||||
SB(SB_AA64_RESET_LOW) = entry | 1;
|
||||
|
|
|
|||
|
|
@ -20,10 +20,10 @@
|
|||
#include "../utils/types.h"
|
||||
|
||||
/*! Flow controller registers. */
|
||||
#define LOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define LOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
#define LOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||
#define LOW_CTLR_HALT_CPU3_EVENTS 0x24
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||
#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS 0x4
|
||||
#define FLOW_CTLR_CPU0_CSR 0x8
|
||||
#define FLOW_CTLR_CPU1_CSR 0x18
|
||||
|
|
|
|||
|
|
@ -36,7 +36,12 @@
|
|||
#define FUSE_DISABLEREGPROGRAM 0x2C
|
||||
#define FUSE_WRITE_ACCESS_SW 0x30
|
||||
#define FUSE_PWR_GOOD_SW 0x34
|
||||
#define FUSE_SKU_INFO 0x110
|
||||
#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c
|
||||
#define FUSE_PRIVATE_KEY0 0x1A4
|
||||
#define FUSE_PRIVATE_KEY1 0x1A8
|
||||
#define FUSE_PRIVATE_KEY2 0x1AC
|
||||
#define FUSE_PRIVATE_KEY3 0x1B0
|
||||
|
||||
/*! Fuse commands. */
|
||||
#define FUSE_READ 0x1
|
||||
|
|
|
|||
|
|
@ -19,6 +19,8 @@
|
|||
#define _PMC_H_
|
||||
|
||||
/*! PMC registers. */
|
||||
#define APBDEV_PMC_CNTRL 0x0
|
||||
#define PMC_CNTRL_MAIN_RST (1 << 4)
|
||||
#define APBDEV_PMC_SEC_DISABLE 0x4
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
|
||||
#define APBDEV_PMC_PWRGATE_STATUS 0x38
|
||||
|
|
@ -27,6 +29,7 @@
|
|||
#define APBDEV_PMC_SCRATCH1 0x54
|
||||
#define APBDEV_PMC_SCRATCH20 0xA0
|
||||
#define APBDEV_PMC_PWR_DET_VAL 0xE4
|
||||
#define PMC_PWR_DET_SDMMC1_IO_EN (1 << 12)
|
||||
#define APBDEV_PMC_DDR_PWR 0xE8
|
||||
#define APBDEV_PMC_CRYPTO_OP 0xF4
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
|
||||
|
|
@ -34,6 +37,7 @@
|
|||
#define APBDEV_PMC_IO_DPD_REQ 0x1B8
|
||||
#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
|
||||
#define APBDEV_PMC_VDDP_SEL 0x1CC
|
||||
#define APBDEV_PMC_DDR_CFG 0x1D0
|
||||
#define APBDEV_PMC_SCRATCH49 0x244
|
||||
#define APBDEV_PMC_TSC_MULT 0x2B4
|
||||
#define APBDEV_PMC_SEC_DISABLE2 0x2C4
|
||||
|
|
@ -44,6 +48,7 @@
|
|||
#define APBDEV_PMC_SECURE_SCRATCH32 0x360
|
||||
#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
|
||||
#define APBDEV_PMC_CNTRL2 0x440
|
||||
#define APBDEV_PMC_IO_DPD3_REQ 0x45C
|
||||
#define APBDEV_PMC_IO_DPD4_REQ 0x464
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
|
||||
#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
|
||||
|
|
|
|||
|
|
@ -56,8 +56,9 @@
|
|||
#define MC_BASE 0x70019000
|
||||
#define EMC_BASE 0x7001B000
|
||||
#define MIPI_CAL_BASE 0x700E3000
|
||||
#define I2S_BASE 0x702D1000
|
||||
#define CL_DVFS_BASE 0x70110000
|
||||
#define I2S_BASE 0x702D1000
|
||||
#define TZRAM_BASE 0x7C010000
|
||||
|
||||
#define _REG(base, off) *(vu32 *)((base) + (off))
|
||||
|
||||
|
|
@ -99,6 +100,9 @@
|
|||
#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
|
||||
#define TEST_REG(off) _REG(0x0, off)
|
||||
|
||||
/*! EVP registers. */
|
||||
#define EVP_CPU_RESET_VECTOR 0x100
|
||||
|
||||
/*! Misc registers. */
|
||||
#define APB_MISC_PP_STRAPPING_OPT_A 0x08
|
||||
#define APB_MISC_PP_PINMUX_GLOBAL 0x40
|
||||
|
|
@ -115,7 +119,40 @@
|
|||
#define SB_AA64_RESET_LOW 0x30
|
||||
#define SB_AA64_RESET_HIGH 0x34
|
||||
|
||||
/*! SYSCTR0 registers. */
|
||||
#define SYSCTR0_CNTFID0 0x20
|
||||
/*! RTC registers. */
|
||||
#define APBDEV_RTC_SECONDS 0x8
|
||||
#define APBDEV_RTC_SHADOW_SECONDS 0xC
|
||||
#define APBDEV_RTC_MILLI_SECONDS 0x10
|
||||
|
||||
/*! TMR registers. */
|
||||
#define TIMERUS_CNTR_1US (0x10 + 0x0)
|
||||
#define TIMERUS_USEC_CFG (0x10 + 0x4)
|
||||
#define TIMER_TMR9_TMR_PTV 0x80
|
||||
#define TIMER_EN (1 << 31)
|
||||
#define TIMER_PER_EN (1 << 30)
|
||||
#define TIMER_WDT4_CONFIG (0x100 + 0x80)
|
||||
#define TIMER_SRC(TMR) (TMR & 0xF)
|
||||
#define TIMER_PER(PER) ((PER & 0xFF) << 4)
|
||||
#define TIMER_SYSRESET_EN (1 << 14)
|
||||
#define TIMER_PMCRESET_EN (1 << 15)
|
||||
#define TIMER_WDT4_COMMAND (0x108 + 0x80)
|
||||
#define TIMER_START_CNT (1 << 0)
|
||||
#define TIMER_CNT_DISABLE (1 << 1)
|
||||
#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
|
||||
#define TIMER_MAGIC_PTRN 0xC45A
|
||||
|
||||
/*! I2S registers. */
|
||||
#define I2S1_CG 0x88
|
||||
#define I2S1_CTRL 0xA0
|
||||
#define I2S2_CG 0x188
|
||||
#define I2S2_CTRL 0x1A0
|
||||
#define I2S3_CG 0x288
|
||||
#define I2S3_CTRL 0x2A0
|
||||
#define I2S4_CG 0x388
|
||||
#define I2S4_CTRL 0x3A0
|
||||
#define I2S5_CG 0x488
|
||||
#define I2S5_CTRL 0x4A0
|
||||
#define I2S_CG_SLCG_ENABLE (1 << 0)
|
||||
#define I2S_CTRL_MASTER_EN (1 << 10)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -20,32 +20,33 @@
|
|||
|
||||
u32 get_tmr_s()
|
||||
{
|
||||
return RTC(0x8); //RTC_SECONDS
|
||||
return RTC(APBDEV_RTC_SECONDS);
|
||||
}
|
||||
|
||||
u32 get_tmr_ms()
|
||||
{
|
||||
// The registers must be read with the following order:
|
||||
// -> RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
|
||||
return (RTC(0x10) | (RTC(0xC)<< 10));
|
||||
return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10));
|
||||
}
|
||||
|
||||
u32 get_tmr_us()
|
||||
{
|
||||
return TMR(0x10); //TIMERUS_CNTR_1US
|
||||
return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
|
||||
}
|
||||
|
||||
void msleep(u32 milliseconds)
|
||||
{
|
||||
u32 start = RTC(0x10) | (RTC(0xC)<< 10);
|
||||
while (((RTC(0x10) | (RTC(0xC)<< 10)) - start) <= milliseconds)
|
||||
u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10);
|
||||
while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS)<< 10)) - start) <= milliseconds)
|
||||
;
|
||||
}
|
||||
|
||||
void usleep(u32 microseconds)
|
||||
{
|
||||
u32 start = TMR(0x10);
|
||||
while ((TMR(0x10) - start) <= microseconds)
|
||||
u32 start = TMR(TIMERUS_CNTR_1US);
|
||||
// Casting to u32 is important!
|
||||
while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds)
|
||||
;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue