Name more hardcoded values

ipl/clock.c

@@ -20,33 +20,33 @@
 #include "sdmmc.h"
 
 static const clock_t _clock_uart[] =  {
-	/* UART A */ { 4, 0x10, 0x178, 6, 0, 0 },
+	/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 },
-	/* UART B */ { 4, 0x10, 0x17C, 7, 0, 0 },
+	/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 },
-	/* UART C */ { 8, 0x14, 0x1A0, 0x17, 0, 0 },
+	/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 },
 	/* UART D */ { 0 },
 	/* UART E */ { 0 }
 };
 
 static const clock_t _clock_i2c[] = {
-	/* I2C1 */ { 4, 0x10, 0x124, 0xC, 6, 0 },
+	/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
 	/* I2C2 */ { 0 },
 	/* I2C3 */ { 0 },
 	/* I2C4 */ { 0 },
-	/* I2C5 */ { 8, 0x14, 0x128, 0xF, 6, 0 },
+	/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
 	/* I2C6 */ { 0 }
 };
 
-static clock_t _clock_se = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 };
+static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 };
 
-static clock_t _clock_host1x = { 4, 0x10, 0x180, 0x1C, 4, 3 };
+static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 };
-static clock_t _clock_tsec = { 0xC, 0x18, 0x1F4, 0x13, 0, 2 };
+static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 };
-static clock_t _clock_sor_safe = { 0x2A4, 0x298, 0, 0x1E, 0, 0 };
+static clock_t _clock_sor_safe = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 };
-static clock_t _clock_sor0 = { 0x28C, 0x280, 0, 0x16, 0, 0 };
+static clock_t _clock_sor0 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_RST_SOURCE, 0x16, 0, 0 };
-static clock_t _clock_sor1 = { 0x28C, 0x280, 0x410, 0x17, 0, 2 };
+static clock_t _clock_sor1 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 };
-static clock_t _clock_kfuse = { 8, 0x14, 0, 8, 0, 0 };
+static clock_t _clock_kfuse = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_RST_SOURCE, 8, 0, 0 };
 
-static clock_t _clock_cl_dvfs = { 0x35C, 0x364, 0, 0x1B, 0, 0 };
+static clock_t _clock_cl_dvfs = { CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_RST_CONTROLLER_RST_SOURCE, 0x1B, 0, 0 };
-static clock_t _clock_coresight = { 0xC, 0x18, 0x1D4, 9, 0, 4};
+static clock_t _clock_coresight = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4};
 
 void clock_enable(const clock_t *clk)
 {

ipl/clock.h

@@ -20,7 +20,9 @@
 #include "types.h"
 
 /*! Clock registers. */
+#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
 #define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
 #define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
@@ -32,38 +34,78 @@
 #define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
 #define CLK_RST_CONTROLLER_OSC_CTRL 0x50
+#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
+#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
+#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
+#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
+#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
+#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
 #define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
 #define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
+#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
+#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
+#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
+#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
 #define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
+#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
+#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
+#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
+#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
 #define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
 #define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
 #define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
 #define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
 #define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
 #define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
 #define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
 #define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
 #define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
 #define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
 #define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
+#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
 #define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
+#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
+#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
 #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
 #define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
 #define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
 
 /*! Generic clock descriptor. */
 typedef struct _clock_t

ipl/cluster.h

@@ -20,6 +20,7 @@
 #include "types.h"
 
 /*! Flow controller registers. */
+#define FLOW_CTLR_HALT_COP_EVENTS 0x4
 #define FLOW_CTLR_RAM_REPAIR 0x40
 #define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
 

ipl/di.c

@@ -25,6 +25,7 @@
 #include "max77620.h"
 #include "gpio.h"
 #include "pinmux.h"
+#include "clock.h"
 
 #include "di.inl"
 
@@ -45,14 +46,14 @@ void display_init()
 	i2c_send_byte(I2C_5, 0x3C, MAX77620_REG_GPIO7, 0x09);
 
 	//Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks.
-	CLOCK(0x30C) = 0x1010000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;
-	CLOCK(0x328) = 0x1010000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;
-	CLOCK(0x304) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
-	CLOCK(0x320) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000;
-	CLOCK(0x284) = 0x20000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;
-	CLOCK(0x66C) = 0xA;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL) = 0xA;
-	CLOCK(0x448) = 0x80000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;
-	CLOCK(0x620) = 0xA;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 0xA;
 
 	//DPD idle.
 	PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
@@ -183,10 +184,10 @@ void display_end()
 	//sleep(10000);
 
 	//Disable clocks.
-	CLOCK(0x308) = 0x1010000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;
-	CLOCK(0x32C) = 0x1010000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;
-	CLOCK(0x300) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
-	CLOCK(0x324) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000;
 
 	DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
 	DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;*/

ipl/hos.c

@@ -548,9 +548,9 @@ int hos_launch(ini_sec_t *cfg)
 	//Signal to pkg2 ready and continue boot.
 	*mb_in = bootStatePkg2Continue;
 
-	//Halt ourselves in waitevent state.
+	//Halt ourselves in waitevent state and resume if there's JTAG activity.
 	while (1)
-		FLOW_CTLR(0x4) = 0x50000000;
+		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = 0x50000000;
 
 	return 0;
 }

ipl/main.c

@@ -221,11 +221,11 @@ void config_pmc_scratch()
 
 void mbist_workaround()
 {
-	CLOCK(0x410) = (CLOCK(0x410) | 0x8000) & 0xFFFFBFFF;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
-	CLOCK(0xD0) |= 0x40800000u;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000u;
-	CLOCK(0x2AC) = 0x40;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;
-	CLOCK(0x294) = 0x40000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;
-	CLOCK(0x304) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
 	sleep(2);
 
 	I2S(0x0A0) |= 0x400;
@@ -242,9 +242,9 @@ void mbist_workaround()
 	VIC(0x8C) = 0xFFFFFFFF;
 	sleep(2);
 
-	CLOCK(0x2A8) = 0x40;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;
-	CLOCK(0x300) = 0x18000000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
-	CLOCK(0x290) = 0x40000;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000;
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0;
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130;
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200;
@@ -252,16 +252,16 @@ void mbist_workaround()
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC;
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780;
 	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300;
-	CLOCK(0xF8) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
-	CLOCK(0xFC) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
-	CLOCK(0x3A0) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
-	CLOCK(0x3A4) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
-	CLOCK(0x554) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
-	CLOCK(0xD0) &= 0x1F7FFFFF;
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF;
-	CLOCK(0x410) &= 0xFFFF3FFF;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF;
-	CLOCK(0x148) = (CLOCK(0x148) & 0x1FFFFFFF) | 0x80000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000;
-	CLOCK(0x180) = (CLOCK(0x180) & 0x1FFFFFFF) | 0x80000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000;
-	CLOCK(0x6A0) = (CLOCK(0x6A0) & 0x1FFFFFFF) | 0x80000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000;
 }
 
 void config_se_brom()
@@ -312,8 +312,8 @@ void config_hw()
 	clock_enable_i2c(I2C_1);
 	clock_enable_i2c(I2C_5);
 
-	static const clock_t clock_unk1 = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 };
+	static const clock_t clock_unk1 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 };
-	static const clock_t clock_unk2 = { 0x358, 0x360, 0, 0x1E, 0, 0 };
+	static const clock_t clock_unk2 = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0, 0x1E, 0, 0 };
 	clock_enable(&clock_unk1);
 	clock_enable(&clock_unk2);
 

ipl/mc.c

@@ -102,7 +102,7 @@ void mc_config_carveout()
 
 void mc_enable_ahb_redirect()
 {
-	CLOCK(0x3A4) = (CLOCK(0x3A4) & 0xFFF7FFFF) | 0x80000;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000;
 	//MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE;
 	MC(MC_IRAM_BOM) = 0x40000000;
 	MC(MC_IRAM_TOM) = 0x4003F000;

ipl/sdram.c

@@ -23,6 +23,7 @@
 #include "fuse.h"
 #include "max77620.h"
 #include "sdram_param_t210.h"
+#include "clock.h"
 
 #define CONFIG_SDRAM_COMPRESS_CFG
 
@@ -51,12 +52,12 @@ static void _sdram_config(const sdram_params_t *params)
 	PMC(APBDEV_PMC_WEAK_BIAS) = 0;
 	sleep(1);
 
-	CLOCK(0x98) = params->pllm_setup_control;
+	CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control;
-	CLOCK(0x9C) = 0;
+	CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0;
-	CLOCK(0x90) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
+	CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | 0x40000000 | ((params->pllm_post_divider & 0xFFFF) << 20);
 
 	u32 wait_end = TMR(0x10) + 300;
-	while (!(CLOCK(0x90) & 0x8000000))
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000))
 	{
 		if (TMR(0x10) >= wait_end)
 			goto break_nosleep;
@@ -64,14 +65,14 @@ static void _sdram_config(const sdram_params_t *params)
 	sleep(10);
 break_nosleep:
 
-	CLOCK(0x19C) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF);
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF);
 	if (params->emc_clock_source_dll)
-		CLOCK(0x664) = params->emc_clock_source_dll;
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll;
 	if (params->clear_clock2_mc1)
-		CLOCK(0x44C) = 0x40000000;
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000;
-	CLOCK(0x328) = 0x2000001;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x2000001;
-	CLOCK(0x284) = 0x4000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x4000;
-	CLOCK(0x30C) = 0x2000001;
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x2000001;
 	EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0;
 	EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1;
 	EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2;