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mtc: Confine RAM OC completely inside minerva
Enabling OVERCLOCK_FREQ takes care of everything without the need of changing minerva caller.
This commit is contained in:
parent
afb749560a
commit
8ce5d55eb8
1 changed files with 31 additions and 13 deletions
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@ -28,6 +28,9 @@
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#define EPRINTF(...)
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#define EPRINTF(...)
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#define EPRINTFARGS(...)
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#define EPRINTFARGS(...)
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#define MAX_FREQ_T210 1600000
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//#define OVERCLOCK_FREQ 1862400
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bool emc_2X_clk_src_is_pllmb;
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bool emc_2X_clk_src_is_pllmb;
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bool fsp_for_src_freq;
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bool fsp_for_src_freq;
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bool train_ram_patterns;
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bool train_ram_patterns;
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@ -3751,14 +3754,17 @@ u32 _minerva_do_periodic_compensation(emc_table_t *mtc_table_entry)
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u32 _minerva_set_rate(mtc_config_t *mtc_cfg)
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u32 _minerva_set_rate(mtc_config_t *mtc_cfg)
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{
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{
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s32 src_emc_entry_idx = 0;
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u32 src_emc_entry_idx = 999;
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s32 dst_emc_entry_idx = 999;
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u32 dst_emc_entry_idx = 999;
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u32 selected_clk_src_emc;
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u32 selected_clk_src_emc;
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u32 selected_emc_2x_clk_src;
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u32 selected_emc_2x_clk_src;
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bool freq_changed = false;
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bool freq_changed = false;
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emc_table_t *src_emc_entry;
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emc_table_t *src_emc_entry;
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emc_table_t *dst_emc_entry;
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emc_table_t *dst_emc_entry;
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if (mtc_cfg->table_entries > 900)
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return 4;
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for (u32 i = 0; i < mtc_cfg->table_entries; i++)
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for (u32 i = 0; i < mtc_cfg->table_entries; i++)
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{
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{
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u32 table_entry_rate = mtc_cfg->mtc_table[i].rate_khz;
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u32 table_entry_rate = mtc_cfg->mtc_table[i].rate_khz;
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@ -3768,6 +3774,12 @@ u32 _minerva_set_rate(mtc_config_t *mtc_cfg)
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dst_emc_entry_idx = i;
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dst_emc_entry_idx = i;
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}
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}
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if (src_emc_entry_idx >= mtc_cfg->table_entries)
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return 4;
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if (dst_emc_entry_idx >= mtc_cfg->table_entries)
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return 4;
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src_emc_entry = (emc_table_t *)&mtc_cfg->mtc_table[src_emc_entry_idx];
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src_emc_entry = (emc_table_t *)&mtc_cfg->mtc_table[src_emc_entry_idx];
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dst_emc_entry = (emc_table_t *)&mtc_cfg->mtc_table[dst_emc_entry_idx];
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dst_emc_entry = (emc_table_t *)&mtc_cfg->mtc_table[dst_emc_entry_idx];
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@ -3776,9 +3788,6 @@ u32 _minerva_set_rate(mtc_config_t *mtc_cfg)
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u32 src_clk_src_emc = src_emc_entry->clk_src_emc;
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u32 src_clk_src_emc = src_emc_entry->clk_src_emc;
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u32 dst_clk_src_emc = dst_emc_entry->clk_src_emc;
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u32 dst_clk_src_emc = dst_emc_entry->clk_src_emc;
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if (mtc_cfg->table_entries > 900)
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return 4;
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freq_changed = _check_freq_changed(dst_rate_khz, dst_clk_src_emc, src_rate_khz, src_clk_src_emc);
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freq_changed = _check_freq_changed(dst_rate_khz, dst_clk_src_emc, src_rate_khz, src_clk_src_emc);
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EPRINTFARGS("Requested freq change from %d to %d.", src_rate_khz, dst_rate_khz);
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EPRINTFARGS("Requested freq change from %d to %d.", src_rate_khz, dst_rate_khz);
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@ -3882,15 +3891,16 @@ void _minerva_init(mtc_config_t *mtc_cfg, void* bp)
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return;
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return;
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}
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}
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// If this is set, it needs to be managed. Changing freq from OC to a lower
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#ifdef OVERCLOCK_FREQ
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// must have the rate_from set to 2131200 and not 1600000
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// Change max rate in table.
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// bool overclock = true;
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mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz = OVERCLOCK_FREQ;
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// if (overclock && mtc_cfg->rate_to == 1600000)
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// Change rates for OC RAM.
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// {
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if (mtc_cfg->rate_from == MAX_FREQ_T210)
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// mtc_cfg->rate_to = 2131200;
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mtc_cfg->rate_from = OVERCLOCK_FREQ;
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// mtc_cfg->mtc_table[9].rate_khz = 2131200;
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if (mtc_cfg->rate_to == MAX_FREQ_T210)
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// }
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mtc_cfg->rate_to = OVERCLOCK_FREQ;
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#endif
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switch (mtc_cfg->train_mode)
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switch (mtc_cfg->train_mode)
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{
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{
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@ -3916,6 +3926,14 @@ void _minerva_init(mtc_config_t *mtc_cfg, void* bp)
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break;
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break;
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}
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}
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#ifdef OVERCLOCK_FREQ
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// Restore rates for OC RAM.
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if (mtc_cfg->rate_from == OVERCLOCK_FREQ)
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mtc_cfg->rate_from = MAX_FREQ_T210;
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if (mtc_cfg->rate_to == OVERCLOCK_FREQ)
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mtc_cfg->rate_to = MAX_FREQ_T210;
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#endif
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mtc_cfg->train_ram_patterns = train_ram_patterns;
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mtc_cfg->train_ram_patterns = train_ram_patterns;
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mtc_cfg->fsp_for_src_freq = fsp_for_src_freq;
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mtc_cfg->fsp_for_src_freq = fsp_for_src_freq;
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mtc_cfg->emc_2X_clk_src_is_pllmb = emc_2X_clk_src_is_pllmb;
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mtc_cfg->emc_2X_clk_src_is_pllmb = emc_2X_clk_src_is_pllmb;
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