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tsec: Don't disable HOST1x clock because it's used
Tsec keys function always disabled host1x clock after running.
This interferes with display interface and disables further window frame syncing.
Display_end code already handles disable and reset of said clock.
It also fixes an ancient bug that was mitigated by removing the 5 frame sync on HOST1X_SYNC_SYNCPT_9 at channel 0:
5fd9daa364 (diff-6b0c56eab8515465d559ff0ea73a22c3L152)
This commit is contained in:
parent
4c09454bca
commit
c5b64a2b58
5 changed files with 28 additions and 20 deletions
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@ -71,6 +71,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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// Enable clocks.
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// Enable clocks.
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clock_enable_host1x();
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clock_enable_host1x();
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usleep(2);
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clock_enable_tsec();
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clock_enable_tsec();
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clock_enable_sor_safe();
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clock_enable_sor_safe();
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clock_enable_sor0();
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clock_enable_sor0();
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@ -175,7 +176,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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}
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}
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// Execute firmware.
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// Execute firmware.
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HOST1X(0x3300) = 0x34C2E1DA;
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTVEC) = 0;
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TSEC(TSEC_BOOTVEC) = 0;
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@ -252,7 +253,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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}
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}
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// Fetch result.
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// Fetch result.
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HOST1X(0x3300) = 0;
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0;
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u32 buf[4];
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u32 buf[4];
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buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
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buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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@ -277,7 +278,6 @@ out:;
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clock_disable_sor0();
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clock_disable_sor0();
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clock_disable_sor_safe();
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clock_disable_sor_safe();
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clock_disable_tsec();
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clock_disable_tsec();
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clock_disable_host1x();
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bpmp_mmu_enable();
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bpmp_mmu_enable();
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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@ -101,6 +101,11 @@
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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#define HOST1X_CH0_SYNC_BASE 0x2100
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#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4)
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#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
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/*! EVP registers. */
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/*! EVP registers. */
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#define EVP_CPU_RESET_VECTOR 0x100
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#define EVP_CPU_RESET_VECTOR 0x100
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@ -693,8 +693,6 @@ static void _create_text_button(lv_theme_t *th, lv_obj_t *parent, lv_obj_t *btn,
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lv_btn_set_action(btn, LV_BTN_ACTION_CLICK, action);
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lv_btn_set_action(btn, LV_BTN_ACTION_CLICK, action);
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}
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}
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static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent)
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static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent)
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{
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{
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lv_obj_t * lbl_credits = lv_label_create(parent, NULL);
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lv_obj_t * lbl_credits = lv_label_create(parent, NULL);
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@ -71,6 +71,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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// Enable clocks.
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// Enable clocks.
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clock_enable_host1x();
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clock_enable_host1x();
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usleep(2);
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clock_enable_tsec();
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clock_enable_tsec();
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clock_enable_sor_safe();
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clock_enable_sor_safe();
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clock_enable_sor0();
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clock_enable_sor0();
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@ -175,7 +176,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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}
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}
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// Execute firmware.
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// Execute firmware.
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HOST1X(0x3300) = 0x34C2E1DA;
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_STATUS) = 0;
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1.
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TSEC(TSEC_BOOTVEC) = 0;
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TSEC(TSEC_BOOTVEC) = 0;
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@ -252,7 +253,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
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}
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}
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// Fetch result.
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// Fetch result.
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HOST1X(0x3300) = 0;
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HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0;
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u32 buf[4];
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u32 buf[4];
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buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
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buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB);
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB);
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@ -277,7 +278,6 @@ out:;
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clock_disable_sor0();
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clock_disable_sor0();
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clock_disable_sor_safe();
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clock_disable_sor_safe();
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clock_disable_tsec();
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clock_disable_tsec();
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clock_disable_host1x();
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bpmp_mmu_enable();
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bpmp_mmu_enable();
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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bpmp_clk_rate_set(BPMP_CLK_SUPER_BOOST);
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@ -101,6 +101,11 @@
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
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#define TEST_REG(off) _REG(0x0, off)
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#define TEST_REG(off) _REG(0x0, off)
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/* HOST1X registers. */
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#define HOST1X_CH0_SYNC_BASE 0x2100
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#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4)
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#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
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/*! EVP registers. */
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/*! EVP registers. */
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#define EVP_CPU_RESET_VECTOR 0x100
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#define EVP_CPU_RESET_VECTOR 0x100
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