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https://github.com/CTCaer/hekate.git
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hos: Automate some eks and bis checks
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parent
94235dd005
commit
ce156ab4e7
5 changed files with 26 additions and 12 deletions
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@ -56,7 +56,7 @@ extern volatile nyx_storage_t *nyx_str;
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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*/
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void _config_oscillators()
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static void _config_oscillators()
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{
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency.
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency.
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@ -79,7 +79,7 @@ void _config_oscillators()
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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}
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void _config_gpios()
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static void _config_gpios()
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{
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{
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// Clamp inputs when tristated.
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// Clamp inputs when tristated.
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APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
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APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
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@ -123,14 +123,14 @@ void _config_gpios()
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// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
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// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
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}
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}
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void _config_pmc_scratch()
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static void _config_pmc_scratch()
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{
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{
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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}
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}
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void _mbist_workaround()
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static void _mbist_workaround()
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{
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{
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// Make sure Audio clocks are enabled before accessing I2S.
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// Make sure Audio clocks are enabled before accessing I2S.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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@ -232,13 +232,14 @@ void _mbist_workaround()
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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}
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}
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void _config_se_brom()
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static void _config_se_brom()
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{
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{
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// Enable fuse clock.
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// Enable fuse clock.
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clock_enable_fuse(true);
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clock_enable_fuse(true);
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// Skip SBK/SSK if sept was run.
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// Skip SBK/SSK if sept was run.
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if (!(b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN))
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bool sbk_skip = b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN || FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF;
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if (!sbk_skip)
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{
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{
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// Bootrom part we skipped.
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// Bootrom part we skipped.
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u32 sbk[4] = {
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u32 sbk[4] = {
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@ -268,7 +269,7 @@ void _config_se_brom()
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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}
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void _config_regulators()
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static void _config_regulators()
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{
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{
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// Disable low battery shutdown monitor.
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config(false);
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max77620_low_battery_monitor_config(false);
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@ -269,6 +269,10 @@ void hos_eks_save(u32 kb)
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u8 *keys = (u8 *)calloc(0x1000, 1);
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u8 *keys = (u8 *)calloc(0x1000, 1);
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se_get_aes_keys(keys + 0x800, keys, 0x10);
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se_get_aes_keys(keys + 0x800, keys, 0x10);
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// Set SBK back.
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if (FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF)
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se_aes_key_set(14, keys + 14 * 0x10, 0x10);
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// Set magic and personalized info.
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// Set magic and personalized info.
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h_cfg.eks->magic = HOS_EKS_MAGIC;
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h_cfg.eks->magic = HOS_EKS_MAGIC;
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h_cfg.eks->enabled[key_idx] = kb;
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h_cfg.eks->enabled[key_idx] = kb;
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@ -48,6 +48,7 @@ void set_default_configuration()
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h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN;
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h_cfg.sept_run = EMC(EMC_SCRATCH0) & EMC_SEPT_RUN;
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h_cfg.aes_slots_new = false;
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h_cfg.aes_slots_new = false;
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h_cfg.rcm_patched = fuse_check_patched_rcm();
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h_cfg.rcm_patched = fuse_check_patched_rcm();
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h_cfg.sbk_set = FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF;
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h_cfg.emummc_force_disable = false;
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h_cfg.emummc_force_disable = false;
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sd_power_cycle_time_start = 0;
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sd_power_cycle_time_start = 0;
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@ -37,6 +37,7 @@ typedef struct _hekate_config
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bool aes_slots_new;
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bool aes_slots_new;
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bool emummc_force_disable;
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bool emummc_force_disable;
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bool rcm_patched;
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bool rcm_patched;
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bool sbk_set;
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u32 errors;
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u32 errors;
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hos_eks_mbr_t *eks;
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hos_eks_mbr_t *eks;
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} hekate_config;
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} hekate_config;
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@ -214,6 +214,10 @@ void hos_eks_save(u32 kb)
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u8 *keys = (u8 *)calloc(0x1000, 1);
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u8 *keys = (u8 *)calloc(0x1000, 1);
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se_get_aes_keys(keys + 0x800, keys, 0x10);
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se_get_aes_keys(keys + 0x800, keys, 0x10);
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// Set SBK back.
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if (h_cfg.sbk_set)
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se_aes_key_set(14, keys + 14 * 0x10, 0x10);
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// Set magic and personalized info.
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// Set magic and personalized info.
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h_cfg.eks->magic = HOS_EKS_MAGIC;
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h_cfg.eks->magic = HOS_EKS_MAGIC;
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h_cfg.eks->enabled[key_idx] = kb;
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h_cfg.eks->enabled[key_idx] = kb;
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@ -659,6 +663,8 @@ void hos_bis_keys_clear()
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se_aes_key_clear(i);
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se_aes_key_clear(i);
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// Set SBK back.
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// Set SBK back.
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if (!h_cfg.sbk_set)
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{
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u32 sbk[4] = {
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u32 sbk[4] = {
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FUSE(FUSE_PRIVATE_KEY0),
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FUSE(FUSE_PRIVATE_KEY0),
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FUSE(FUSE_PRIVATE_KEY1),
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FUSE(FUSE_PRIVATE_KEY1),
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@ -671,3 +677,4 @@ void hos_bis_keys_clear()
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// Lock SBK from being read.
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// Lock SBK from being read.
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se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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}
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}
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}
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