mirrors/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate.git synced 2024-11-22 18:06:40 +00:00
Code Issues Releases Activity

lib: minerva: add Samsung 8GB support

Browse source 
And remove frequencies smaller than deep sleep frequency from the tables.
This commit is contained in:
CTCaer 2023-06-08 04:50:59 +03:00
parent 9d8ebc7e38
commit d8d15bde44
3 changed files with 42 additions and 1851 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
modules/hekate_libsys_minerva/mtc.h
View file

@ -44,9 +44,9 @@
#define EMC_CH1(off) _REG(EMC1_BASE, off)
/* End of addresses and access macros */
#define EMC_TABLE_SIZE_R7 49280
#define EMC_TABLE_ENTRY_SIZE_R7 4928
#define EMC_TABLE_ENTRY_SIZE_R3 4300
#define EMC_TABLE_SIZE_R7 (EMC_TABLE_ENTRY_SIZE_R7 * 7)
#define EMC_STATUS_UPDATE_TIMEOUT 1000
#define EMC_PERIODIC_TRAIN_MS 100
#define EMC_TEMP_COMP_MS 1000

1853
modules/hekate_libsys_minerva/mtc_switch_tables.h
View file

File diff suppressed because it is too large Load diff

38
modules/hekate_libsys_minerva/sys_sdrammtc.c
View file

@ -3822,6 +3822,8 @@ static u32 _minerva_set_rate(mtc_config_t *mtc_cfg)
static void _minerva_get_table(mtc_config_t *mtc_cfg)
{
memset(mtc_cfg->mtc_table, 0, EMC_TABLE_ENTRY_SIZE_R7 * 10);
switch (mtc_cfg->sdram_id)
{
case DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN:
@ -3831,8 +3833,44 @@ static void _minerva_get_table(mtc_config_t *mtc_cfg)
case DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT:
case DRAM_4GB_COPPER_SAMSUNG:
case DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH:
case DRAM_8GB_SAMSUNG_K4FBE3D4HM_MGXX:
default:
memcpy(mtc_cfg->mtc_table, nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7);
if (mtc_cfg->sdram_id == DRAM_8GB_SAMSUNG_K4FBE3D4HM_MGXX)
{
for (u32 i = 0; i < EMC_TABLE_SIZE_R7 / EMC_TABLE_ENTRY_SIZE_R7; i++)
{
emc_table_t *table = &mtc_cfg->mtc_table[i];
u32 period = 1000000000 / table->rate_khz;
table->burst_regs.emc_rfc = 280000 / period;
table->shadow_regs_ca_train.emc_rfc = 280000 / period;
table->shadow_regs_quse_train.emc_rfc = 280000 / period;
table->shadow_regs_rdwr_train.emc_rfc = 280000 / period;
table->burst_regs.emc_rfcpb = 140000 / period;
table->shadow_regs_ca_train.emc_rfcpb = 140000 / period;
table->shadow_regs_quse_train.emc_rfcpb = 140000 / period;
table->shadow_regs_rdwr_train.emc_rfcpb = 140000 / period;
table->burst_regs.emc_txsr = 287500 / period;
table->shadow_regs_ca_train.emc_txsr = 287500 / period;
table->shadow_regs_quse_train.emc_txsr = 287500 / period;
table->shadow_regs_rdwr_train.emc_txsr = 287500 / period;
table->burst_regs.emc_txsrdll = table->burst_regs.emc_txsr;
table->shadow_regs_ca_train.emc_txsrdll = table->shadow_regs_ca_train.emc_txsr;
table->shadow_regs_quse_train.emc_txsrdll = table->shadow_regs_quse_train.emc_txsr;
table->shadow_regs_rdwr_train.emc_txsrdll = table->shadow_regs_rdwr_train.emc_txsr;
table->burst_regs.emc_dyn_self_ref_control &= 0x7FFFFFFF;
table->shadow_regs_ca_train.emc_dyn_self_ref_control &= 0x7FFFFFFF;
table->shadow_regs_quse_train.emc_dyn_self_ref_control &= 0x7FFFFFFF;
table->shadow_regs_rdwr_train.emc_dyn_self_ref_control &= 0x7FFFFFFF;
table->dram_timings.t_rfc = 280;
}
}
break;
}