13 commits

Author	SHA1	Message	Date
CTCaer	f5040f1e41	Update and add missing copyrights ... Probably more need to change.	2020-03-14 09:24:24 +02:00
CTCaer	c99a87dd09	clock: Move PLLC config from bpmp.c to clock.c	2020-01-07 06:46:22 +02:00
CTCaer	009db77426	bpmp: Switch to PLLC for SCLK/BPMP clock source	2020-01-07 06:26:29 +02:00
CTCaer	7604239237	bpmp: Update driver to latest	2019-12-14 22:21:42 +02:00
CTCaer	f256bd5909	Move all I/DRAM addresses into a memory map ... Many addresses were moved around to pack the memory usage!	2019-12-08 02:23:03 +02:00
Kostas Missos	0b45a5a11a	bpmp: Reduce freq to 589MHz ... 3 users had issues with 602MHz. This will probably bring the SoC binning compatibility to 100%. Additionally, make it easy to change default boost frequency. The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)	2019-12-07 02:01:29 +02:00
Kostas Missos	bc7dec2e61	bpmp: Add forcable maintenance ... + Fix build issues	2019-12-07 01:47:44 +02:00
CTCaer	a8d529cf6a	Refactoring and comment adding	2019-09-12 23:08:38 +03:00
Kostas Missos	718e502983	Add more register names + refactoring	2019-09-09 16:56:37 +03:00
CTCaer	f622d57f6b	utils: Fix ms timer accuracy ... Additionally add BPMP delay timers for future use.	2019-08-28 01:33:38 +03:00
ctcaer@gmail.com	138da26a9a	[BPMP] Fix cache coherency issues ... + Fix framebuffer memfetcher for some SoC revisions.	2019-07-06 22:22:47 +03:00
ctcaer@gmail.com	08b84384a6	Bugfixes and cleanup	2019-07-06 22:08:37 +03:00
ctcaer@gmail.com	03872e814a	[Nyx] Prep hekate main for nyx	2019-06-30 03:55:19 +03:00