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Code Issues Releases Activity
1668 commits 2 branches 75 tags 6.7 MiB
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468 commits

Author SHA1 Message Date
CTCaer
a6727f6e32 bdk: display: update active regs on vsync for WinD 
Doing that on hsync can cause issues on disable without actually syncing to it.
 2024-04-25 04:38:04 +03:00
CTCaer
e846f4576e bdk: minerva: l4t: adjust sdmmc1 la and freq table 
- LA is tightened up
- Copied frequencies are now 204/408/800/1333/1600/OC (from 204/666/800/1600/OC)
 2024-03-29 13:21:53 +02:00
CTCaer
42c02e97e8 bdk: display: add 6.2" panel clone 2024-03-29 13:21:53 +02:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759 bdk: smmu: refactor and update driver 
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
 2024-03-14 09:21:06 +02:00
CTCaer
9ba7c44b89 bdk: clock: use real source clock dividers 
Use CLK_SRC_DIV macro in order to have the actual divider showing.
 2024-03-13 02:01:01 +02:00
CTCaer
9a520d63a6 bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
CTCaer
20e661fc01 bdk: refactor flow control defines 2024-03-13 01:50:45 +02:00
CTCaer
3a4fa12f42 bdk: smmu: powergate ccplex after enabling smmu 2024-03-13 01:44:58 +02:00
CTCaer
fb31cb2926 bdk: ccplex: add no rst vector lock & powergating 
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
 2024-03-13 01:37:52 +02:00
CTCaer
f126486266 bdk: sdmmc: utilize block size defines 2024-03-12 15:47:14 +02:00
CTCaer
25b7ffecd1 bdk: fatfs: always align malloc to lba 2024-03-12 15:43:44 +02:00
CTCaer
7d1600b85c bdk: consolidate ffsystem into bdk 2024-03-12 15:16:18 +02:00
CTCaer
83ac40c4b9 bdk: rtc: handle offset adjustment in-place 2024-03-12 15:08:55 +02:00
CTCaer
4131ff12d7 bdk: sdram: adjust sdmmc1 la for l4t 2024-02-21 10:50:15 +02:00
CTCaer
9ea847578e bdk: display: add another oem clone 2024-02-21 10:40:46 +02:00
CTCaer
6d69ef3cf6 bdk: sprintf: allow padding > 9 2024-02-16 16:01:54 +02:00
CTCaer
f05563579e bdk: max77620: raise sd1 max voltage 
For T210.
 2024-02-16 15:55:40 +02:00
CTCaer
644747230c bdk: dram: add FPGA code for 3rd gen micron 2024-02-16 15:54:22 +02:00
CTCaer
1f30b8deb7 bdk: minerva: add custom option in table 2024-02-16 15:51:02 +02:00
CTCaer
bfc6069b2d bdk: display: add OEM panel id 2024-02-14 00:08:06 +02:00
CTCaer
4576ed81ef sdram: acquire per chip mrr info 2024-02-12 04:08:39 +02:00
CTCaer
b37430dc1d bdk: update copyright year 2024-01-07 12:38:10 +02:00
CTCaer
75543875e2 bdk: mc: remove some redundant carveout cfg 2024-01-07 12:33:29 +02:00
CTCaer
30c320d6e7 bdk: sdram: update all ram info comments 2024-01-06 22:05:24 +02:00
CTCaer
eff27d92f2 bdk: sdram: update default wpr overrides 
Since it's only used in L4T set them to the correct latest reg tool values.

HOS overrides them anyway.
 2024-01-06 22:03:54 +02:00
CTCaer
3874840d77 bdk: sdram: update cfg for 8GB erista 2024-01-06 21:59:18 +02:00
CTCaer
74e252aaf2 bdk: sdram: update latest reg tool vpr overrides 
Set them to default config and remove them from patching.
 2024-01-06 21:58:51 +02:00
CTCaer
c7333e710c bdk: strtol: support unsigned 32bit hex 
If base is 16 and input is not negative allow unsigned 32bit parsing.

This allows parsing numbers of up to 4294967295 in that case.
 2024-01-06 21:55:21 +02:00
CTCaer
dab5eb9aa0 bdk: sprintf: do not accept null chars 
Skip NULL chars on putc since they break the resulted string.
 2024-01-06 21:52:48 +02:00
CTCaer
92093ff08e bdk: se: deduplicate sha hash extraction 2023-12-27 21:07:52 +02:00
CTCaer
2cc6cd45d9 bdk: dram: small refactor 2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b bdk: sdram: refactor patching offsets 2023-12-27 21:04:04 +02:00
CTCaer
bb6e4deb4c bdk: remove unused lp0 cfg from bdk 2023-12-27 21:02:33 +02:00
CTCaer
41d3565353 bdk: sdmmc: deduplicate function modes get 
And parse the whole info
 2023-12-27 15:01:20 +02:00
CTCaer
b584a3f53a bdk: add several defines 2023-12-25 04:08:34 +02:00
CTCaer
7f98fb736a bdk: hwinit: reorder sdmmc1 reg disable 2023-12-25 04:07:26 +02:00
CTCaer
87c50732c0 bdk: fuse: simplify idle wait 2023-12-25 03:47:26 +02:00
CTCaer
504659a39b bdk: actmon: switch to averaged sampling 2023-12-25 03:46:05 +02:00
CTCaer
e47a819948 bdk: se: add more useful functions 
- aes cmac 128bit
- aes hashing
- option to clear updated aes iv
 2023-12-25 03:44:52 +02:00
CTCaer
913cdee8e8 bdk: sdram: rename 3rd gen t210b01 hynix ram 
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
 2023-12-25 03:02:11 +02:00
CTCaer
eff55ff378 bdk: touch: rename samsung touch panel 
BH2109 is the board model and not the touch panel.
 2023-12-25 02:41:42 +02:00
CTCaer
09dfcfc57d bdk: display: deduplicate interrupt code 2023-12-25 02:40:38 +02:00
CTCaer
239c48c790 bdk: usb: hid: improve stick calibration 
Wait a bit before calibrating stick centers, in order to avoid bad values.
 2023-12-25 02:37:40 +02:00
CTCaer
ce137852b7 bdk: change some defines and comments 2023-10-12 06:59:15 +03:00
CTCaer
ce42e27f45 bdk: minerva: do not handle oc freq 
Arachne already handles it.
 2023-08-22 16:44:41 +03:00
CTCaer
d73a3fdd7c bdk: sdram: name 1a micron ram chips 
Again, as with 3rd gen samsung and hynix, that's an educated guess.
 2023-08-22 14:44:27 +03:00
CTCaer
fdf0dcc636 bdk: joycon: add info about sio imu report 2023-08-22 14:36:23 +03:00
CTCaer
f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer
1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer
f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer
9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer
b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer
d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer
820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer
93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer
191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer
8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer
18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00
CTCaer
c2ee6be2f5 bdk: sdram: add Samsung 8GB RAM support for T210 
And remove Copper support completely.
 2023-06-08 04:16:51 +03:00
CTCaer
73a133556d bdk: sdram: correct sku related info 
Validated so rename accordingly.
 2023-06-08 02:57:30 +03:00
CTCaer
7d3663616e bdk: sdram: name 2 of the new ram chips 
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
 2023-06-08 02:52:03 +03:00
CTCaer
e76aebabba bdk: mem: minerva: check table size in clock check 
Don't hardcode table size to 10.
 2023-06-08 02:45:34 +03:00
CTCaer
bc0eea11f3 bdk: joycon: add calibration struct 2023-06-08 02:44:35 +03:00
CTCaer
795b4ad26e bdk: sdmmc: increase bw priority to SDMMC1 for L4T 2023-04-06 17:30:01 +03:00
CTCaer
bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer
811fa4c88b bdk: sdmmc: add SD registers debug printing 
Can be enabled with `SDMMC_DEBUG_PRINT_SD_REGS`
 2023-04-06 10:13:35 +03:00
CTCaer
8528e6a08a bdk: util: do not edit rtc alarm in power function 2023-03-31 09:12:58 +03:00
CTCaer
27ae312227 bdk: minor naming edits 2023-03-31 09:11:55 +03:00
CTCaer
50811aacfa bdk: touch: reorder power on 
So touch IC reset can be properly done on a fast power cycle.
 2023-03-31 09:08:20 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support 
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
 2023-03-31 08:54:13 +03:00
CTCaer
7f32c6d211 bdk: sd: better removal detection handling 2023-03-31 08:31:20 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
29e32f09fb bdk: sdmmc: properly identify sdmmc1 clk config 
Remove schmitt trigger config from clock pin on sdmmc1 for identifying previous pinmuxing state.
 2023-03-31 08:27:48 +03:00
CTCaer
b123571c56 bdk: sdmmc: only allow power raise if SDR50 and up 
As per spec.
 2023-03-31 08:26:19 +03:00
CTCaer
b7164a629f bdk: sdmmc: allow max power limit to be set 
Even if it defaults to 1.44W.
Some cards' firmware maybe be bugged.

The 3.3V regulator on all SKUs allow more than 800mA current anyway.
 2023-03-31 08:24:52 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support 
But disable it by default in the auto selection.
 2023-03-31 08:23:10 +03:00
CTCaer
76a5facbc3 bdk: clock: rename clock_t to clk_rst_t 
To avoid redefines when standard math header is used.
 2023-03-31 08:18:45 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
5e134ed54b bdk: sdmmc: refactor defines 2023-03-31 08:00:14 +03:00
CTCaer
4cfe5f241e bdk: sdmmc: remove eMMC OC 
Additionally, the flag BDK_SDMMC_OC_AND_EXTRA_PRINT is now just BDK_SDMMC_EXTRA_PRINT
 2023-03-31 07:55:17 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
107fbd1d24 bdk: gpio: add debounce set function 
The debounce time is not per pin but per bank. So software should manage proper time for sibling pins
 2023-03-31 07:43:16 +03:00
CTCaer
1edb6583ac bdk: gpio: reorder gpio config 
Since there are some bootloaders that mess with the states of some power gpios, reorder gpio configuration for input/output in order to prevent power pin glitches.
 2023-03-31 07:41:50 +03:00
CTCaer
d286ee4e9d bdk: sd: only clear inserted when requested 
Also rename var to further explain its usage
 2023-02-23 01:25:05 +02:00
CTCaer
17cdd5af0d bdk: hwdeinit: restore order of bpmp clock set 
Restore order of bpmp clock scale down in deinit, in order to decrease pressure on clock deinits.
 2023-02-22 14:48:43 +02:00
CTCaer
55e01ca735 bdk: sd: improve init error handling 
- Management of sd init done is now on sd init retry function
 Also manages inserted, since it can set the sd init done to false if failed
- Init will now always check if SD is also initialized, since it doesn't manage it anymore. Because of that, mounting is no longer forced, but checked first.
- Unmount/End will now always set the sd as unmounted, since no data residue is expected after the fact

The above will improve handling of faulty SD cards or faulty SD readers.
 2023-02-22 13:19:12 +02:00
CTCaer
c279fa2521 bdk: max77621: ckkadv is basically an enum 2023-02-22 13:00:36 +02:00
CTCaer
9a98c1afb9 bdk: stylistic corrections 
And update copyrights
 2023-02-11 23:46:38 +02:00
CTCaer
72abe60a3b bdk: hw init: remove support for broken hwinits 
It's 2023 already.
 2023-02-11 23:19:56 +02:00
CTCaer
ee682fdf24 bdk: l4t: minerva: don't rely on UB 2023-02-11 23:17:27 +02:00
CTCaer
42859a2373 bdk: usb: ums: print errors when sdmmc init fails 2023-02-11 23:16:37 +02:00
CTCaer
22bdd0e0ff bdk: sdmmc: remove unused power limits 
Also name some magic numbers
 2023-02-11 23:15:28 +02:00