CTCaer
d687b53249
bdk: heap: add zalloc and utilize it
2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759
bdk: smmu: refactor and update driver
...
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
2024-03-14 09:21:06 +02:00
CTCaer
9a520d63a6
bdk: smmu: refactor driver and allow other asid
2024-03-13 01:54:46 +02:00
CTCaer
3a4fa12f42
bdk: smmu: powergate ccplex after enabling smmu
2024-03-13 01:44:58 +02:00
CTCaer
fb31cb2926
bdk: ccplex: add no rst vector lock & powergating
...
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
2024-03-13 01:37:52 +02:00
CTCaer
4131ff12d7
bdk: sdram: adjust sdmmc1 la for l4t
2024-02-21 10:50:15 +02:00
CTCaer
644747230c
bdk: dram: add FPGA code for 3rd gen micron
2024-02-16 15:54:22 +02:00
CTCaer
1f30b8deb7
bdk: minerva: add custom option in table
2024-02-16 15:51:02 +02:00
CTCaer
4576ed81ef
sdram: acquire per chip mrr info
2024-02-12 04:08:39 +02:00
CTCaer
b37430dc1d
bdk: update copyright year
2024-01-07 12:38:10 +02:00
CTCaer
75543875e2
bdk: mc: remove some redundant carveout cfg
2024-01-07 12:33:29 +02:00
CTCaer
30c320d6e7
bdk: sdram: update all ram info comments
2024-01-06 22:05:24 +02:00
CTCaer
eff27d92f2
bdk: sdram: update default wpr overrides
...
Since it's only used in L4T set them to the correct latest reg tool values.
HOS overrides them anyway.
2024-01-06 22:03:54 +02:00
CTCaer
3874840d77
bdk: sdram: update cfg for 8GB erista
2024-01-06 21:59:18 +02:00
CTCaer
74e252aaf2
bdk: sdram: update latest reg tool vpr overrides
...
Set them to default config and remove them from patching.
2024-01-06 21:58:51 +02:00
CTCaer
2cc6cd45d9
bdk: dram: small refactor
2023-12-27 21:06:09 +02:00
CTCaer
a6ec41744b
bdk: sdram: refactor patching offsets
2023-12-27 21:04:04 +02:00
CTCaer
bb6e4deb4c
bdk: remove unused lp0 cfg from bdk
2023-12-27 21:02:33 +02:00
CTCaer
913cdee8e8
bdk: sdram: rename 3rd gen t210b01 hynix ram
...
Confirmed to be a Hynix H54G46CYRBX267 and not a H9HCNNNBKMMLXR-NEI
2023-12-25 03:02:11 +02:00
CTCaer
ce42e27f45
bdk: minerva: do not handle oc freq
...
Arachne already handles it.
2023-08-22 16:44:41 +03:00
CTCaer
d73a3fdd7c
bdk: sdram: name 1a micron ram chips
...
Again, as with 3rd gen samsung and hynix, that's an educated guess.
2023-08-22 14:44:27 +03:00
CTCaer
1cc97ebc51
bdk: update various comments
2023-07-31 17:03:15 +03:00
CTCaer
b9bc35a22e
bdk: dram: correct old comments
2023-07-21 18:39:46 +03:00
CTCaer
93ed4d0899
bdk: emc: add temp and feature reporting defines
2023-06-09 10:38:24 +03:00
CTCaer
c2ee6be2f5
bdk: sdram: add Samsung 8GB RAM support for T210
...
And remove Copper support completely.
2023-06-08 04:16:51 +03:00
CTCaer
73a133556d
bdk: sdram: correct sku related info
...
Validated so rename accordingly.
2023-06-08 02:57:30 +03:00
CTCaer
7d3663616e
bdk: sdram: name 2 of the new ram chips
...
Not actually validated, but educated guess, since all previous one were correct in the end.
New Micron still unknown, can be guessed but model doesn't exist in any public list.
2023-06-08 02:52:03 +03:00
CTCaer
e76aebabba
bdk: mem: minerva: check table size in clock check
...
Don't hardcode table size to 10.
2023-06-08 02:45:34 +03:00
CTCaer
795b4ad26e
bdk: sdmmc: increase bw priority to SDMMC1 for L4T
2023-04-06 17:30:01 +03:00
CTCaer
9a98c1afb9
bdk: stylistic corrections
...
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
4e15e034b8
bdk: sdram: remove (lp)ddr2/3 support
2023-02-11 22:44:31 +02:00
CTCaer
560f077196
bdk: sdram: rename new dram chips
2022-12-19 05:25:26 +02:00
CTCaer
2ea595e98d
bdk: sdram: add new dram ids/configs
...
On T210B01 dram ids 7 and 16 got removed.
29 to 34 were added.
Additionally, remove all deprecated and unused dram id enums.
2022-10-11 10:38:43 +03:00
CTCaer
c52c11e7bc
bdk: mem: improve emc MRR reading
2022-10-11 03:51:12 +03:00
CTCaer
70523e404f
bdk: whitespace refactor
2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108
bdk: migrate timers/sleeps to timer driver
2022-06-27 10:22:19 +03:00
CTCaer
2c768db542
bdk: heap: add nodes info
2022-05-19 14:53:02 +03:00
CTCaer
37de367fef
bdk: sdram: deduplicate dram configs
...
Additionally add info about new hynix chip and correct ids 3 and 5 on T210B01 based Switch.
2022-05-08 04:58:36 +03:00
CTCaer
83c95d8a3b
bdk: sdram: update 20/21/22 ids for new dram
...
Dram chip is Samsung 4GB built on 1z-nm that allows for 40% lower power usage.
2022-03-23 02:20:55 +02:00
CTCaer
ff214f25c1
bdk: update l4t hekatf prep functions
2022-03-23 00:58:20 +02:00
CTCaer
83b895a062
bdk: heap: improvements
...
Correct types everywhere.
Add BDK_MALLOC_NO_DEFRAG that disables defragmentation on the heap.
2022-02-15 00:22:38 +02:00
CTCaer
3f65a30b2e
bdk: more atf prep
2022-02-15 00:14:53 +02:00
CTCaer
9a80f8b4b5
bdk: minerva: fix fsp op/wr check for l4t
2022-01-29 01:31:28 +02:00
CTCaer
ef5790cc2c
bdk: mc: always on ahb arbitration
...
- Removed disables
- SDMMC code now just checks if it has access
2022-01-29 01:29:02 +02:00
CTCaer
8327de8e2e
bdk: replace NYX flag with proper flags
...
- BDK_MINERVA_CFG_FROM_RAM: enables support for getting minerva configuration from nyx storage
- BDK_HW_EXTRA_DEINIT: enables extra deinit in hw_reinit_workaround
- BDK_SDMMC_OC_AND_EXTRA_PRINT: enables eMMC OC support (533 MB/s) and extra error printing
2022-01-20 13:19:48 +02:00
CTCaer
7ae4fd03c2
bdk: minerva: prep for ATF direct boot support
2022-01-20 12:43:24 +02:00
CTCaer
70504c295e
bdk: various functionality independent changes
2022-01-16 01:03:24 +02:00
CTCaer
981c986b3f
bdk: sdram: name the new micron modules
2021-10-19 09:13:14 +03:00
CTCaer
49bcaf3914
bdk: correct some types and warnings
2021-10-15 16:18:06 +03:00
CTCaer
c801ef8dda
bdk: use size defines where applicable
2021-10-01 15:03:18 +03:00
