It will now show erros for the following:
- Missing or old libsys_minerva.bso (DRAM training).
- Missing libsys_lp0.bso (LP0 sleep mode).
- Missing or old Nyx version
This is conditional:
In order to not cancel booting while trying to enter fastboot in android, the combo MUST be initiated with `VOL+` (hold) -> `VOL-` (hold)
The manual optimization done dramatically increases performance in software color blending.
Isolated gains reach 20-30%.
Color blending calculates 2 +1 color channels instead of the expensive 1+1+1 calculations.
This is as best as it gets without going in asm optimizations.
- Removing no-inline produces 30-50% performance gains on specific real time sensitive functions used for rendering.
On overall, this will give 5-10% observed performance gains.
- Strict aliasing produces some extra small gains.
Perf gains from removing LTO linker flag amounts to actually more than 5% average in real usage scenarios in Nyx.
(These include overall timings with static waits included. So basically as observed by user.)
Gains observed, on many isolated cases, were between 15-35%.
Additionally, this will make compiling fast again.
3 users had issues with 602MHz.
This will probably bring the SoC binning compatibility to 100%.
Additionally, make it easy to change default boost frequency.
The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)
There's an increasing ammount of users that kill their batteries when forgetting their devices into AutoRCM / RCM mode.
This will now force a shutdown the moment the battery reaches 2.8V. Even if device is inside RCM mode.
Notice: We might need to increase the limit.
- Training and switch is now faster
- Compatibility checks: New Minerva does not allow old binaries. New binaries do not allow old Minerva
- MTC table is now in a safe region
- Periodic training period increased to every 250ms
- Allow reuse of unused sections that fit exactly to selected allocation size. Decreases fragmentation dramatically.
- Always allocate and align mapped memory to selected alignment. Avoids having fragmented unused maps that are not aligned.
- Use a static alignment based on BPMP and generally average cache line size. Boosts performance when MMU is used.
Allow the patch loop to end via empty source data as per original spec and error out on 0 length if source data is not null.
emuMMC force decompression patch safely avoids that.
- Allow SHA to calculate sizes > 16MB and refactor sha function
- Name various registers and magic numbers
- Fix various key access bugs
In a later commit this new design will boost verification times significantly and also allow full SHA256 hashes.
