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44 commits

Author SHA1 Message Date
CTCaer
48334779a5 bdk: sdmmc: error reporting changes
- Correct transfer error message
- Add debug print for deinit
2024-06-08 17:41:11 +03:00
CTCaer
85eb5489fe bdk: pmc: rename io/det power defines 2024-06-08 12:16:07 +03:00
CTCaer
a34206df5b bdk: sdmmc: small changes
- Log warning for comp pad calibration timeout
- Rename some func/defines
- Increase SDMMC1 power disable wait to 10ms
 No real perceived functionality change.
2024-06-07 17:09:30 +03:00
CTCaer
9d79af231e bdk: use static where it should 2024-06-02 07:09:34 +03:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses
And simplify relevant drivers that hardcoded them.
2023-07-31 16:59:15 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
bb10b8aea3 bdk: sdmmc: small refactor 2023-04-06 10:19:53 +03:00
CTCaer
f4bf48e76a bdk: sdmmc: add driver type set support 2023-03-31 09:04:10 +03:00
CTCaer
d258c82d52 bdk: sdmmc: add UHS DDR200 support
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 08:54:13 +03:00
CTCaer
2f7e841b50 bdk: sdmmc: move sdr12 setup for better readability 2023-03-31 08:29:20 +03:00
CTCaer
29e32f09fb bdk: sdmmc: properly identify sdmmc1 clk config
Remove schmitt trigger config from clock pin on sdmmc1 for identifying previous pinmuxing state.
2023-03-31 08:27:48 +03:00
CTCaer
25be98b7e3 bdk: sdmmc: add UHS DDR50 support
But disable it by default in the auto selection.
2023-03-31 08:23:10 +03:00
CTCaer
502fc1ed50 bdk: sdmmc: rename ddr100 to the actual HS100 name 2023-03-31 08:15:40 +03:00
CTCaer
5e134ed54b bdk: sdmmc: refactor defines 2023-03-31 08:00:14 +03:00
CTCaer
4cfe5f241e bdk: sdmmc: remove eMMC OC
Additionally, the flag BDK_SDMMC_OC_AND_EXTRA_PRINT is now just BDK_SDMMC_EXTRA_PRINT
2023-03-31 07:55:17 +03:00
CTCaer
9a222e0e49 bdk: sdmmc: rename divisor param to card clock 2023-03-31 07:53:46 +03:00
CTCaer
298893f404 bdk: sdmmc: remove powersave arg from sdmmc init 2023-03-31 07:51:43 +03:00
CTCaer
1ce5bb10f8 bdk: sdmmc: refactor debug prints 2023-03-31 07:49:26 +03:00
CTCaer
9a98c1afb9 bdk: stylistic corrections
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
5bb9a244ea bdk: utilize new gpio functions 2023-02-11 23:08:32 +02:00
CTCaer
4d823d5909 bdk: slight refactor 2022-12-19 05:22:55 +02:00
CTCaer
6257d20db9 bdk: emmc: add emmc_set_partition
Additionally, add SDMMC index info to errors.
2022-12-19 04:53:50 +02:00
CTCaer
197ce4c76f bdk: sdmmc: timing changes
- Correct HS102 naming to DDR100
- Fix clock for DDR50 (even if it's unused)
2022-10-11 04:05:12 +03:00
CTCaer
70523e404f bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108 bdk: migrate timers/sleeps to timer driver 2022-06-27 10:22:19 +03:00
CTCaer
76d1b4e221 bdk: sdmmc: refactor defines
And fix a bug with tuning trim values
2022-05-08 05:21:29 +03:00
CTCaer
7c74391754 bdk: bpmp: do not use full maintenance
Instead use proper clean/invalidation of dcache.
2022-02-15 00:14:14 +02:00
CTCaer
8327de8e2e bdk: replace NYX flag with proper flags
- BDK_MINERVA_CFG_FROM_RAM: enables support for getting minerva configuration from nyx storage
- BDK_HW_EXTRA_DEINIT: enables extra deinit in hw_reinit_workaround
- BDK_SDMMC_OC_AND_EXTRA_PRINT: enables eMMC OC support (533 MB/s) and extra error printing
2022-01-20 13:19:48 +02:00
CTCaer
10e1f67dc5 bdk: utils: add strcpy with head/tail whitespace removal 2022-01-20 12:36:25 +02:00
CTCaer
d368b93fdd sdmmc: move error prints checks inside ifdefs 2021-09-17 23:12:54 +03:00
CTCaer
38f456a2ee sdmmc: Refactor again
- Refactor various variables and defines
- Removed Card/BGA and OEM ID info as they are static and useless
- Commented out bkops functions completely as not used
- Remove extra buf usage when there's already storage for storing that data
- Optimize various functions to save space
- Clean up useless or duplicate code
2021-02-06 03:41:35 +02:00
CTCaer
f6a3b2c9ac sdmmc: Ensure writes gone through after disabling io power 2021-01-14 17:53:22 +02:00
CTCaer
745ac609d2 max7762x: Update everything to use the improved pmic management 2021-01-04 02:41:15 +02:00
CTCaer
ba984d02eb sdmmc: Mitigate some Phison SDs which think they are SDSC 2020-12-11 17:43:01 +02:00
CTCaer
5b8fb9fb6b Various refactoring and addition of comments 2020-12-11 17:25:59 +02:00
CTCaer
c13eabcde8 sdmmc: Add T210B01 support
The driver was working before this, but adding the changes provides a proper and better sdmmc controller inner state.
2020-12-02 02:07:15 +02:00
CTCaer
cabaa6cfb8 Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
CTCaer
89a4eadab0 sdmmc: Refactor some names 2020-11-26 01:08:42 +02:00
CTCaer
1f5b371608 Refactor some names
Additionally:
- Do not retry to init sd if all modes failed in Nyx.
- Do not try to read/write if sdmmc controller and card are not initialized.
2020-10-23 06:32:24 +03:00
CTCaer
7b03a24196 sdmmc: Add extra error printing 2020-08-15 13:16:37 +03:00
CTCaer
82da1aaf2a sdmmc: Correct name of bus speed 14 2020-07-17 17:38:01 +03:00
CTCaer
6e256d29c7 Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
CTCaer
185526d134 Introducing Bootloader Development Kit (BDK)
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.

Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.

Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.

This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00
Renamed from bootloader/storage/sdmmc_driver.c (Browse further)