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489 commits 2 branches 75 tags 6.7 MiB
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3 commits

Author SHA1 Message Date
CTCaer
a52af1bf41 Fix building on make 4.3 2020-03-04 01:34:35 +02:00
Kostas Missos
7c42f72b8a refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
Kostas Missos
cae9044c17 Minerva our DRAM trainer 
Supports up to 1600MHz and periodic training.

For more check here: https://github.com/CTCaer/minerva_tc
 2018-11-04 03:15:32 +02:00