CTCaer
8bf3bee08b
bdk: uart: fix fifo clear
...
- Do not clear fifo for everything if not needed
- Correct fifo clear checks
2024-10-04 21:52:24 +03:00
CTCaer
f2be59888b
bdk: add irq header to bdk header
2024-10-04 21:48:44 +03:00
CTCaer
5c77601f7a
bdk: ums: always allow finish reply
...
Parse scsi cmd failures are handled internally.
2024-10-04 21:47:26 +03:00
CTCaer
9e239df39e
bdk: constify various args
2024-10-04 21:45:57 +03:00
CTCaer
b1bc6ebdd8
bdk: joycon: utilize packet id per joycon
...
Also fix a possible infinite loop
2024-10-04 21:39:35 +03:00
CTCaer
716cfbfbaf
bdk: sdram: refactor init
2024-07-02 18:02:05 +03:00
CTCaer
e47b6ec19b
bdk: hwinit: display changes
...
Do not display ldo0 if enabled here as it's not needed.
Make sure PLLP_OUTB is properly reset in case of coming out of warmboot.
2024-07-02 17:59:14 +03:00
CTCaer
acb3997a7d
bdk: hwinit: reorder no io power
...
And make sure sdmmc iopower is not enabled after vdd disable.
2024-07-02 17:56:20 +03:00
CTCaer
4c5cc6d567
bdk: display: small refactor
2024-07-02 17:52:12 +03:00
CTCaer
75a4a8ba1d
bdk: sdmmc: remove higher power limits
...
UHS-I Cards force a max of 1.44W even if higher modes are selected.
This does not change functionality, so remove them as unused.
2024-06-10 13:37:28 +03:00
CTCaer
a37b5c7841
bdk: sdmmc: no need to raise power limit for HS25
2024-06-10 13:24:07 +03:00
CTCaer
48334779a5
bdk: sdmmc: error reporting changes
...
- Correct transfer error message
- Add debug print for deinit
2024-06-08 17:41:11 +03:00
CTCaer
054c68f251
bdk: hwinit: power on all relevant rails
...
Since that doesn't happen via sdram init anymore, do it in hwinit.
It only matters if we came out of warmboot.
2024-06-08 12:21:15 +03:00
CTCaer
655209bedc
bdk: sdram: keep sdmmc1 no iopower state
2024-06-08 12:19:24 +03:00
CTCaer
85eb5489fe
bdk: pmc: rename io/det power defines
2024-06-08 12:16:07 +03:00
CTCaer
8b4f776c9d
bdk: fan: rename functions and add set from temp
...
- Rename functions to proper style (drivername_)
- Add fan_set_from_temp for managing the fan with passed SoC temperature.
2024-06-07 17:14:05 +03:00
CTCaer
a34206df5b
bdk: sdmmc: small changes
...
- Log warning for comp pad calibration timeout
- Rename some func/defines
- Increase SDMMC1 power disable wait to 10ms
No real perceived functionality change.
2024-06-07 17:09:30 +03:00
CTCaer
4a24fe0b35
bdk: display: add useful functions
...
- Window disable
- Window framebuffer address set
- Window framebuffer move to new address
2024-06-06 06:27:30 +03:00
CTCaer
14c482ddce
bdk: display: remove max77620 gpio 7 enable
...
It is actually not used at all.
So do not configure it to save power.
2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33
bdk: hwinit: move LDO8 init in regulators init
...
And also reorder it above I2C1 init (because of HOAG).
2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab
bdk: hwinit: move sd2 to hw init
...
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
2024-06-05 01:33:15 +03:00
CTCaer
7652d9cdb1
bdk: display: use mipi cal sw war on T210 also
...
As per Nvidia, the pad brick separates clock and data terminations.
This necessitates doing the calibration twice.
Nvidia/Nintendo probably never updated that part on T210 since it's from around
2015/2016. T210B01 is based on 2017 codebase so it has it.
HOS (nvservices, not boot) is probably updated to also do that.
If not, then they should fix it.
There are 0 known issue reports with that on T210, but well.
2024-06-05 01:11:04 +03:00
CTCaer
48ef1826e9
bdk: display: rename functions
...
display_init_framebuffer_pitch -> display_init_window_a_pitch
display_init_framebuffer_pitch_vic -> display_init_window_a_pitch_vic
display_init_framebuffer_pitch_inv -> display_init_window_a_pitch_inv
display_init_framebuffer_block -> display_init_window_a_block
display_init_framebuffer_log -> display_init_window_d_console
display_activate_console -> display_window_d_console_enable
display_deactivate_console -> display_window_d_console_disable
display_init_cursor -> display_cursor_init
display_set_pos_cursor -> display_cursor_set_pos
display_deinit_cursor -> display_cursor_deinit
2024-06-05 01:00:58 +03:00
CTCaer
4fef1890aa
bdk: rename exec_cfg to reg_write_array
...
And cfg_op_t to reg_cfg_t.
2024-06-05 00:49:15 +03:00
CTCaer
320b91a767
bdk: display: return duty for oled panel properly
...
For display_get_backlight_brightness.
2024-06-02 08:23:58 +03:00
CTCaer
c5f6837c35
bdk: display: wait 1 frame after display off cmd
2024-06-02 08:23:13 +03:00
CTCaer
72f980d0f4
bdk: display: fully streamline dc/win setup
...
As explained before, Nvidia just grabbed the whole dynamic init and made arrays
of it, without actually optimizing it.
The second part of the streamline aims to fully de-duplicate that.
- Completely remove all already set registers for DC/DISP/WIN.
- Do not touch other windows when a specific window is setup.
- Init Window D also together with A/B/C since code is made for DISPA.
- Add missing increase for syncpt 1.
2024-06-02 08:22:20 +03:00
CTCaer
b3be7e7a41
bdk: display: use the same HS exit threshold
...
No need to use minimum on T210.
Use the same byte clocks as T210B01 to simplify init.
2024-06-02 08:11:22 +03:00
CTCaer
26c6c6372d
bdk: display: rename window setup arrays
...
Add window number info and remove the fb naming
2024-06-02 08:05:50 +03:00
CTCaer
28eb3f4bcd
bdk: display: deduplicate array size macro
2024-06-02 08:02:44 +03:00
CTCaer
bd55a3e756
bdk: clock: always set DISPA source
...
No need to distinguish between LP or HS.
Setting the same value doesn't glitch.
2024-06-02 08:00:42 +03:00
CTCaer
b01cc2432f
bdk: irq: remove ack source
...
HW interrupts can't be managed by FIR.
Only actual hw can clear the interrupt.
2024-06-02 07:46:18 +03:00
CTCaer
05db43a97c
bdk: hwinit: move down debug uart init
2024-06-02 07:44:22 +03:00
CTCaer
859811a154
bdk: fatfs: update copyright
...
Last edit was in 2022.
2024-06-02 07:42:35 +03:00
CTCaer
6b54c4a477
bdk: usb: hid: don't send a packet if no new data
...
Reduce the interrupt caused at the host side
2024-06-02 07:40:11 +03:00
CTCaer
9d79af231e
bdk: use static where it should
2024-06-02 07:09:34 +03:00
CTCaer
84c5439c70
bdk: usb: utilize apb relaxed clocks for init
2024-06-02 07:01:31 +03:00
CTCaer
8c44969afb
bdk: blz: refactor style
2024-06-02 06:51:47 +03:00
CTCaer
7a74761da9
bdk: bpmp: add and use bpmp_clk_rate_relaxed
2024-06-02 06:51:06 +03:00
CTCaer
14706cef4e
bdk: minerva: add emc src div disable
2024-06-02 06:46:28 +03:00
CTCaer
93296c2c38
bdk: joycon: add packet size checks
...
Pass the real received data size and do the proper checks for minimum info.
2024-05-19 17:42:10 +03:00
CTCaer
a070d2e394
bdk: ums: allow real sizes for boot partitions
...
Since that's eMMC, do not clamp the size to 4MB.
That doesn't affect anything other than allowing the host to see the whole
physical partition .
2024-05-19 10:57:20 +03:00
CTCaer
927489d2da
bdk: add missed defines
2024-05-19 10:50:25 +03:00
CTCaer
ae29f359ee
bdk: hwinit: rename reinit_workaround to deinit
2024-05-19 10:49:25 +03:00
CTCaer
7af343dd6c
bdk: input: make joycon detection more robust
...
There's a hw bug on the gpio controller that can latch the last value on reads.
Mitigate that by reading once to unlatch the input value.
Also actually allow sio to be polled every 8ms.
2024-05-19 10:19:25 +03:00
CTCaer
547a3542ee
bdk: display: add more defines
2024-05-19 10:16:52 +03:00
CTCaer
4bc0a0591c
bdk: display: wait 2us for bl pwm config to take
...
Fixes the tiny blink showing up while pwm is still at max.
2024-05-19 10:15:52 +03:00
CTCaer
985c513770
bdk: hwinit: add arbiter config
2024-05-19 10:07:06 +03:00
CTCaer
16eb6a3c44
bdk: types: do not overflow on byte swaps
...
Addresses warning message.
2024-04-25 16:57:43 +03:00
CTCaer
856994e4f4
bdk: sprintf: add right padding support
2024-04-25 04:56:38 +03:00
