CTCaer
c99a87dd09
clock: Move PLLC config from bpmp.c to clock.c
2020-01-07 06:46:22 +02:00
CTCaer
009db77426
bpmp: Switch to PLLC for SCLK/BPMP clock source
2020-01-07 06:26:29 +02:00
CTCaer
2f43145131
uart: Add invert, get/set IIR and fifo empty functions
2019-12-16 22:16:40 +02:00
CTCaer
e3fca2bce5
uart: Add timeout and len report to uart receive
2019-12-16 22:15:21 +02:00
CTCaer
da112a0ae9
uart: Proper uart init
2019-12-16 22:12:09 +02:00
CTCaer
7604239237
bpmp: Update driver to latest
2019-12-14 22:21:42 +02:00
CTCaer
f256bd5909
Move all I/DRAM addresses into a memory map
...
Many addresses were moved around to pack the memory usage!
2019-12-08 02:23:03 +02:00
CTCaer
0290892b23
nyx hw reconfig: Add fan and 5V regulators deinit
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Additionally re-arrange minerva and mmu after these.
2019-12-08 01:41:57 +02:00
Kostas Missos
48c15a8fde
nyx: Release the shackles
2019-12-07 20:16:38 +02:00
Kostas Missos
0b45a5a11a
bpmp: Reduce freq to 589MHz
...
3 users had issues with 602MHz.
This will probably bring the SoC binning compatibility to 100%.
Additionally, make it easy to change default boost frequency.
The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)
2019-12-07 02:01:29 +02:00
Kostas Missos
bc7dec2e61
bpmp: Add forcable maintenance
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+ Fix build issues
2019-12-07 01:47:44 +02:00
CTCaer
dd8ec0d28b
clock: Always wait 2us before deasserting reset
2019-12-04 21:32:51 +02:00
CTCaer
0b1eebefe1
Small refactor and bugfixes
2019-12-04 21:31:39 +02:00
CTCaer
65fbdfddbf
kfuse: Ensure that kfuse is ready 100% for tsec
2019-10-22 18:57:51 +03:00
Kostas Missos
7c42f72b8a
refactor: Remove all unwanted whitespace
2019-10-18 18:02:06 +03:00
CTCaer
23e246f224
i2c: Add missing clocks + more refactoring
2019-09-12 23:11:17 +03:00
CTCaer
3028568019
pmc-ccplex: Have proper Power Domain toggling
2019-09-12 23:09:38 +03:00
CTCaer
a8d529cf6a
Refactoring and comment adding
2019-09-12 23:08:38 +03:00
CTCaer
c5b64a2b58
tsec: Don't disable HOST1x clock because it's used
...
Tsec keys function always disabled host1x clock after running.
This interferes with display interface and disables further window frame syncing.
Display_end code already handles disable and reset of said clock.
It also fixes an ancient bug that was mitigated by removing the 5 frame sync on HOST1X_SYNC_SYNCPT_9 at channel 0:
5fd9daa364 (diff-6b0c56eab8515465d559ff0ea73a22c3L152)
2019-09-11 02:19:41 +03:00
Kostas Missos
718e502983
Add more register names + refactoring
2019-09-09 16:56:37 +03:00
CTCaer
f622d57f6b
utils: Fix ms timer accuracy
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Additionally add BPMP delay timers for future use.
2019-08-28 01:33:38 +03:00
CTCaer
3472e7e7fb
Various bugfixes
2019-08-28 01:08:57 +03:00
ctcaer@gmail.com
5b919cb12e
[Touch] Fix touch hang for some SoC revisions
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Fixes the hang on Nyx boot.
2019-07-06 22:24:03 +03:00
ctcaer@gmail.com
138da26a9a
[BPMP] Fix cache coherency issues
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+ Fix framebuffer memfetcher for some SoC revisions.
2019-07-06 22:22:47 +03:00
ctcaer@gmail.com
08b84384a6
Bugfixes and cleanup
2019-07-06 22:08:37 +03:00
ctcaer@gmail.com
c41f98039c
[Nyx] Introducing hekate GUI, named Nyx!
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Version 0.8.0.
Expect dragons!
2019-06-30 04:03:00 +03:00
