mirror of
https://github.com/CTCaer/hekate.git
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114 lines
4.3 KiB
C
114 lines
4.3 KiB
C
/*
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* Copyright (c) 2019-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdlib.h>
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#include "payload_00.h"
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#include "payload_01.h"
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#include <memory_map.h>
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#include <libs/compr/lz.h>
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#include <soc/clock.h>
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#include <soc/t210.h>
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// 0x4003D000: Safe for panic preserving, 0x40038000: Safe for debugging needs.
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#define IPL_RELOC_TOP 0x40038000
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#define IPL_PATCHED_RELOC_SZ 0x94
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boot_cfg_t __attribute__((section ("._boot_cfg"))) b_cfg;
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const volatile ipl_ver_meta_t __attribute__((section ("._ipl_version"))) ipl_ver = {
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.magic = BL_MAGIC,
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.version = (BL_VER_MJ + '0') | ((BL_VER_MN + '0') << 8) | ((BL_VER_HF + '0') << 16) | ((BL_VER_RL) << 24),
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.rsvd0 = 0,
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.rsvd1 = 0
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};
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const char __attribute__((section ("._octopus"))) octopus[] =
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"\n"
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" ___\n"
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" .-' `'.\n"
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" / \\\n"
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" | ;\n"
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" | | ___.--,\n"
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" _.._ |0) = (0) | _.---'`__.-( (_.\n"
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" __.--'`_.. '.__.\\ '--. \\_.-' ,.--'` `\"\"`\n"
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" ( ,.--'` ',__ /./; ;, '.__.'` __\n"
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" _`) ) .---.__.' / | |\\ \\__..--\"\" \"\"\"--.,_\n"
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" `---' .'.''-._.-'`_./ /\\ '. \\ _.--''````'''--._`-.__.'\n"
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" | | .' _.-' | | \\ \\ '. `----`\n"
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" \\ \\/ .' \\ \\ '. '-._)\n"
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" \\/ / \\ \\ `=.__`'-.\n"
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" / /\\ `) ) / / `\"\".`\\\n"
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" , _.-'.'\\ \\ / / ( ( / /\n"
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" `--'` ) ) .-'.' '.'. | (\n"
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" (/` ( (` ) ) '-; [switchbrew]\n";
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void loader_main()
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{
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// Preliminary BPMP clocks init.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz).
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
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// Set arbiter.
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ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x12412D1;
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ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x0000000;
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ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x220244A;
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ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320369B;
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// Get Payload size.
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u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size.
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payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add compiler alignment.
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payload_size = ALIGN(payload_size, 4); // Align size to 4 bytes.
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u32 *payload_addr = (u32 *)payload_00;
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// Relocate payload to a safer place.
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u32 words = payload_size >> 2;
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u32 *src = payload_addr + words - 1;
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u32 *dst = (u32 *)(IPL_RELOC_TOP - 4);
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while (words)
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{
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*dst = *src;
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src--;
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dst--;
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words--;
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}
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// Set source address of the first part.
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u8 *src_addr = (void *)(IPL_RELOC_TOP - payload_size);
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// Uncompress first part.
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u32 dst_pos = LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR, sizeof(payload_00));
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// Set source address of the second part. Includes compiler alignment.
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src_addr += (u32)payload_01 - (u32)payload_00;
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// Uncompress second part.
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LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR + dst_pos, sizeof(payload_01));
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// Copy over boot configuration storage.
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memcpy((u8 *)(IPL_LOAD_ADDR + IPL_PATCHED_RELOC_SZ), &b_cfg, sizeof(boot_cfg_t));
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// Chainload into uncompressed payload.
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void (*ipl_ptr)() = (void *)IPL_LOAD_ADDR;
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(*ipl_ptr)();
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// Halt if we managed to get out of execution.
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while (true)
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;
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}
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