mirror of
https://github.com/CTCaer/hekate.git
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262 lines
7.8 KiB
C
262 lines
7.8 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDMMC_DRIVER_H_
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#define _SDMMC_DRIVER_H_
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#include <utils/types.h>
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#include <storage/sdmmc_t210.h>
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/*! SDMMC controller IDs. */
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#define SDMMC_1 0
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#define SDMMC_2 1
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#define SDMMC_3 2
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#define SDMMC_4 3
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/*! SDMMC power types. */
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#define SDMMC_POWER_OFF 0
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#define SDMMC_POWER_1_8 1
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#define SDMMC_POWER_3_3 2
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/*! SDMMC bus widths. */
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#define SDMMC_BUS_WIDTH_1 0
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#define SDMMC_BUS_WIDTH_4 1
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#define SDMMC_BUS_WIDTH_8 2
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/*! SDMMC response types. */
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#define SDMMC_RSP_TYPE_0 0
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#define SDMMC_RSP_TYPE_1 1
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#define SDMMC_RSP_TYPE_2 2
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#define SDMMC_RSP_TYPE_3 3
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#define SDMMC_RSP_TYPE_4 4
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#define SDMMC_RSP_TYPE_5 5
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/*! SDMMC mask interrupt status. */
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#define SDMMC_MASKINT_MASKED 0
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#define SDMMC_MASKINT_NOERROR -1
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#define SDMMC_MASKINT_ERROR -2
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/*! SDMMC present state. */
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#define SDHCI_CMD_INHIBIT 0x1
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#define SDHCI_DATA_INHIBIT 0x2
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#define SDHCI_DOING_WRITE 0x100
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#define SDHCI_DOING_READ 0x200
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#define SDHCI_SPACE_AVAILABLE 0x400
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#define SDHCI_DATA_AVAILABLE 0x800
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#define SDHCI_CARD_PRESENT 0x10000
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#define SDHCI_CD_STABLE 0x20000
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#define SDHCI_CD_LVL 0x40000
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#define SDHCI_WRITE_PROTECT 0x80000
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#define SDHCI_DATA_LVL_MASK 0xF00000
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#define SDHCI_DATA_0_LVL_MASK 0x100000
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#define SDHCI_CMD_LVL 0x1000000
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/*! SDMMC transfer mode. */
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#define SDHCI_TRNS_DMA 0x01
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#define SDHCI_TRNS_BLK_CNT_EN 0x02
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#define SDHCI_TRNS_AUTO_CMD12 0x04
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#define SDHCI_TRNS_AUTO_CMD23 0x08
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#define SDHCI_TRNS_AUTO_SEL 0x0C
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#define SDHCI_TRNS_WRITE 0x00
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#define SDHCI_TRNS_READ 0x10
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#define SDHCI_TRNS_MULTI 0x20
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/*! SDMMC command. */
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#define SDHCI_CMD_RESP_MASK 0x3
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#define SDHCI_CMD_RESP_NO_RESP 0x0
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#define SDHCI_CMD_RESP_LEN136 0x1
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#define SDHCI_CMD_RESP_LEN48 0x2
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#define SDHCI_CMD_RESP_LEN48_BUSY 0x3
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#define SDHCI_CMD_CRC 0x08
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#define SDHCI_CMD_INDEX 0x10
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#define SDHCI_CMD_DATA 0x20
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#define SDHCI_CMD_ABORTCMD 0xC0
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/*! SDMMC host control. */
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#define SDHCI_CTRL_LED 0x01
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#define SDHCI_CTRL_4BITBUS 0x02
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#define SDHCI_CTRL_HISPD 0x04
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#define SDHCI_CTRL_DMA_MASK 0x18
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#define SDHCI_CTRL_SDMA 0x00
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#define SDHCI_CTRL_ADMA1 0x08
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#define SDHCI_CTRL_ADMA32 0x10
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#define SDHCI_CTRL_ADMA64 0x18
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#define SDHCI_CTRL_8BITBUS 0x20
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#define SDHCI_CTRL_CDTEST_INS 0x40
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#define SDHCI_CTRL_CDTEST_EN 0x80
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/*! SDMMC host control 2. */
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#define SDHCI_CTRL_UHS_MASK 0xFFF8
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#define SDHCI_CTRL_VDD_180 8
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#define SDHCI_CTRL_DRV_TYPE_B 0x00
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#define SDHCI_CTRL_DRV_TYPE_A 0x10
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#define SDHCI_CTRL_DRV_TYPE_C 0x20
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#define SDHCI_CTRL_DRV_TYPE_D 0x30
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#define SDHCI_CTRL_EXEC_TUNING 0x40
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#define SDHCI_CTRL_TUNED_CLK 0x80
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#define SDHCI_HOST_VERSION_4_EN 0x1000
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#define SDHCI_ADDRESSING_64BIT_EN 0x2000
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#define SDHCI_CTRL_PRESET_VAL_EN 0x8000
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/*! SDMMC power control. */
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#define SDHCI_POWER_ON 0x01
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#define SDHCI_POWER_180 0x0A
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#define SDHCI_POWER_300 0x0C
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#define SDHCI_POWER_330 0x0E
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#define SDHCI_POWER_MASK 0xF1
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// /*! SDMMC max current. */
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// #define SDHCI_MAX_CURRENT_330_MASK 0xFF
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// #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
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// #define SDHCI_MAX_CURRENT_MULTIPLIER 4
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/*! SDMMC clock control. */
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#define SDHCI_DIVIDER_SHIFT 8
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#define SDHCI_DIVIDER_HI_SHIFT 6
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#define SDHCI_DIV_MASK 0xFF00
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#define SDHCI_DIV_HI_MASK 0xC0
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#define SDHCI_PROG_CLOCK_MODE 0x20
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#define SDHCI_CLOCK_CARD_EN 0x4
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#define SDHCI_CLOCK_INT_STABLE 0x2
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#define SDHCI_CLOCK_INT_EN 0x1
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/*! SDMMC software reset. */
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#define SDHCI_RESET_ALL 0x01
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#define SDHCI_RESET_CMD 0x02
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#define SDHCI_RESET_DATA 0x04
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/*! SDMMC interrupt status and control. */
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#define SDHCI_INT_RESPONSE 0x1
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#define SDHCI_INT_DATA_END 0x2
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#define SDHCI_INT_BLK_GAP 0x4
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#define SDHCI_INT_DMA_END 0x8
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#define SDHCI_INT_SPACE_AVAIL 0x10
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#define SDHCI_INT_DATA_AVAIL 0x20
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#define SDHCI_INT_CARD_INSERT 0x40
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#define SDHCI_INT_CARD_REMOVE 0x80
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#define SDHCI_INT_CARD_INT 0x100
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#define SDHCI_INT_RETUNE 0x1000
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#define SDHCI_INT_CQE 0x4000
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#define SDHCI_INT_ERROR 0x8000
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/*! SDMMC error interrupt status and control. */
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#define SDHCI_ERR_INT_TIMEOUT 0x1
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#define SDHCI_ERR_INT_CRC 0x2
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#define SDHCI_ERR_INT_END_BIT 0x4
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#define SDHCI_ERR_INT_INDEX 0x8
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#define SDHCI_ERR_INT_DATA_TIMEOUT 0x10
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#define SDHCI_ERR_INT_DATA_CRC 0x20
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#define SDHCI_ERR_INT_DATA_END_BIT 0x40
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#define SDHCI_ERR_INT_BUS_POWER 0x80
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#define SDHCI_ERR_INT_AUTO_CMD_ERR 0x100
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#define SDHCI_ERR_INT_ADMA_ERROR 0x200
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#define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \
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(SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \
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SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \
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SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \
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SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT)
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/*! SD bus speeds. */
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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/*! SDMMC timmings. */
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#define SDHCI_TIMING_MMC_ID 0
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#define SDHCI_TIMING_MMC_LS26 1
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#define SDHCI_TIMING_MMC_HS52 2
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#define SDHCI_TIMING_MMC_HS200 3
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#define SDHCI_TIMING_MMC_HS400 4
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#define SDHCI_TIMING_SD_ID 5
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#define SDHCI_TIMING_SD_DS12 6
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#define SDHCI_TIMING_SD_HS25 7
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#define SDHCI_TIMING_UHS_SDR12 8
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#define SDHCI_TIMING_UHS_SDR25 9
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#define SDHCI_TIMING_UHS_SDR50 10
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#define SDHCI_TIMING_UHS_SDR104 11
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#define SDHCI_TIMING_UHS_SDR82 12 // SDR104 with a 163.2MHz -> 81.6MHz clock.
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#define SDHCI_TIMING_UHS_DDR50 13
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#define SDHCI_TIMING_MMC_HS102 14
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#define SDHCI_CAN_64BIT 0x10000000
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/*! SDMMC Low power features. */
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#define SDMMC_POWER_SAVE_DISABLE 0
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#define SDMMC_POWER_SAVE_ENABLE 1
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/*! Helper for SWITCH command argument. */
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#define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8))
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/*! SDMMC controller context. */
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typedef struct _sdmmc_t
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{
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t210_sdmmc_t *regs;
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u32 id;
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u32 divisor;
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u32 clock_stopped;
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int powersave_enabled;
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int card_clock_enabled;
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int venclkctl_set;
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u32 venclkctl_tap;
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u32 expected_rsp_type;
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u32 dma_addr_next;
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u32 rsp[4];
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u32 rsp3;
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} sdmmc_t;
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/*! SDMMC command. */
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typedef struct _sdmmc_cmd_t
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{
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u16 cmd;
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u32 arg;
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u32 rsp_type;
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u32 check_busy;
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} sdmmc_cmd_t;
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/*! SDMMC request. */
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typedef struct _sdmmc_req_t
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{
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void *buf;
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u32 blksize;
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u32 num_sectors;
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int is_write;
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int is_multi_block;
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int is_auto_cmd12;
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} sdmmc_req_t;
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int sdmmc_get_io_power(sdmmc_t *sdmmc);
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u32 sdmmc_get_bus_width(sdmmc_t *sdmmc);
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void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width);
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void sdmmc_save_tap_value(sdmmc_t *sdmmc);
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int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type);
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void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable);
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int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type);
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int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd);
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int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp);
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bool sdmmc_get_sd_inserted();
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int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable);
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void sdmmc_end(sdmmc_t *sdmmc);
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void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy);
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int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out);
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int sdmmc_enable_low_voltage(sdmmc_t *sdmmc);
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#endif
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