mirror of
https://github.com/CTCaer/hekate.git
synced 2024-11-23 02:16:41 +00:00
147 lines
No EOL
3.6 KiB
C
147 lines
No EOL
3.6 KiB
C
/*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <stdlib.h>
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#include "minerva.h"
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#include "../soc/fuse.h"
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#include "../utils/util.h"
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#include "../soc/clock.h"
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#include "../ianos/ianos.h"
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#include "../soc/fuse.h"
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#include "../soc/t210.h"
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extern volatile nyx_storage_t *nyx_str;
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void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *);
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u32 minerva_init()
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{
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u32 curr_ram_idx = 0;
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minerva_cfg = NULL;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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#ifdef NYX
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// Set table to nyx storage.
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mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
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// Check if Minerva is already initialized.
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if (mtc_cfg->init_done == MTC_INIT_MAGIC)
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{
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mtc_cfg->train_mode = OP_PERIODIC_TRAIN; // Retrain if needed.
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u32 ep_addr = ianos_loader(false, "bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
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minerva_cfg = (void *)ep_addr;
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return 0;
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}
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else
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{
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mtc_config_t mtc_tmp;
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mtc_tmp.mtc_table = mtc_cfg->mtc_table;
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mtc_tmp.sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
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mtc_tmp.init_done = MTC_NEW_MAGIC;
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u32 ep_addr = ianos_loader(false, "bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)&mtc_tmp);
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// Ensure that Minerva is new.
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if (mtc_tmp.init_done == MTC_INIT_MAGIC)
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minerva_cfg = (void *)ep_addr;
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else
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mtc_cfg->init_done = 0;
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// Copy Minerva context to Nyx storage.
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if (minerva_cfg)
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memcpy(mtc_cfg, (void *)&mtc_tmp, sizeof(mtc_config_t));
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}
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#else
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memset(mtc_cfg, 0, sizeof(mtc_config_t));
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// Set table to nyx storage.
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mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table;
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mtc_cfg->sdram_id = (fuse_read_odm(4) >> 3) & 0x1F;
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mtc_cfg->init_done = MTC_NEW_MAGIC; // Initialize mtc table.
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u32 ep_addr = ianos_loader(false, "bootloader/sys/libsys_minerva.bso", DRAM_LIB, (void *)mtc_cfg);
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// Ensure that Minerva is new.
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if (mtc_cfg->init_done == MTC_INIT_MAGIC)
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minerva_cfg = (void *)ep_addr;
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else
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mtc_cfg->init_done = 0;
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#endif
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if (!minerva_cfg)
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return 1;
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// Get current frequency
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for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++)
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{
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if (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc)
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break;
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}
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mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz;
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mtc_cfg->rate_to = 204000;
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mtc_cfg->train_mode = OP_TRAIN;
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minerva_cfg(mtc_cfg, NULL);
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mtc_cfg->rate_to = 800000;
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minerva_cfg(mtc_cfg, NULL);
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mtc_cfg->rate_to = 1600000;
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minerva_cfg(mtc_cfg, NULL);
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// FSP WAR.
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mtc_cfg->train_mode = OP_SWITCH;
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mtc_cfg->rate_to = 800000;
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minerva_cfg(mtc_cfg, NULL);
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// Switch to max.
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mtc_cfg->rate_to = 1600000;
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minerva_cfg(mtc_cfg, NULL);
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return 0;
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}
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void minerva_change_freq(minerva_freq_t freq)
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{
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if (!minerva_cfg)
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return;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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if (mtc_cfg->rate_from != freq)
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{
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mtc_cfg->rate_to = freq;
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mtc_cfg->train_mode = OP_SWITCH;
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minerva_cfg(mtc_cfg, NULL);
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}
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}
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void minerva_periodic_training()
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{
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if (!minerva_cfg)
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return;
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mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg;
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if (mtc_cfg->rate_from == FREQ_1600)
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{
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mtc_cfg->train_mode = OP_PERIODIC_TRAIN;
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minerva_cfg(mtc_cfg, NULL);
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}
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} |