mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-29 11:26:04 +00:00
281 lines
8.6 KiB
C
281 lines
8.6 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "di.h"
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#include "../gfx/gfx.h"
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#include "../power/max77620.h"
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#include "../power/max7762x.h"
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#include "../soc/clock.h"
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#include "../soc/gpio.h"
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#include "../soc/i2c.h"
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#include "../soc/pinmux.h"
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#include "../soc/pmc.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#pragma GCC push_options
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#pragma GCC target ("thumb")
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#pragma GCC optimize ("Os")
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#include "di.inl"
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static u32 _display_ver = 0;
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static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
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{
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u32 end = get_tmr_us() + timeout;
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while (get_tmr_us() < end && DSI(off) & mask)
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;
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usleep(5);
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}
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void display_init()
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{
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// Power on.
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max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
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// Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL) = 0xA;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 0xA;
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// DPD idle.
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PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
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// Config pins.
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;
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gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); // Backlight +-5V.
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gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); // Backlight +-5V.
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
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usleep(10000);
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gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); // Backlight PWM, Enable, Reset.
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gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
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gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Backlight Enable enable.
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// Config display interface and display.
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MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
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exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
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exec_cfg((u32 *)DSI_BASE, _display_config_3, 61);
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usleep(10000);
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH); // Backlight Reset enable.
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usleep(60000);
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x406; // MIPI_DCS_GET_DISPLAY_ID
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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_display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO);
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DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
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_display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA);
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usleep(5000);
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_display_ver = DSI(_DSIREG(DSI_RD_DATA));
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_4, 43);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1105; // MIPI_DCS_EXIT_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(180000);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2905; // MIPI_DCS_SET_DISPLAY_ON
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(20000);
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exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
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exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
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exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);
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usleep(10000);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
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exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);
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usleep(10000);
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
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}
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void display_backlight_pwm_init()
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{
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clock_enable_pwm();
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31); // Enable PWM
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1; // PWM clock source.
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
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}
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void display_backlight(bool enable)
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{
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gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO.
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}
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void display_backlight_brightness(u32 brightness, u32 step_delay)
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{
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u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF;
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if (brightness == old_value)
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return;
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if (brightness > 255)
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brightness = 255;
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if (old_value < brightness)
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{
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for (u32 i = old_value; i < brightness + 1; i++)
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{
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31) | (i << 16); // Enable PWM
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usleep(step_delay);
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}
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}
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else
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{
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for (u32 i = old_value; i > brightness; i--)
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{
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31) | (i << 16); // Enable PWM
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usleep(step_delay);
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}
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}
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if (!brightness)
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PWM(PWM_CONTROLLER_PWM_CSR_0) = 0;
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}
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void display_end()
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{
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display_backlight_brightness(0, 1000);
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 1;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
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exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
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usleep(10000);
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
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DSI(_DSIREG(DSI_WR_DATA)) = 0x1005; // MIPI_DCS_ENTER_SLEEP_MODE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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usleep(50000);
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
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usleep(10000);
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// Disable clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000;
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DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
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DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1;
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}
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void display_color_screen(u32 color)
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{
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8);
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// Configure display to show single color.
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DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0;
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DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0;
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DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
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DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
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DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
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usleep(35000);
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display_backlight(true);
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}
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u32 *display_init_framebuffer()
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{
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// Sanitize framebuffer area.
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//memset((u32 *)FB_ADDRESS, 0, 0x3C0000);
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// This configures the framebuffer @ FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);
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usleep(35000);
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return (u32 *)FB_ADDRESS;
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}
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u32 *display_init_framebuffer2()
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{
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// Sanitize framebuffer area.
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memset((u32 *)FB_ADDRESS, 0, 0x3C0000);
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// This configures the framebuffer @ FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer2, 32);
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usleep(35000);
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return (u32 *)FB_ADDRESS;
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}
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#pragma GCC pop_options
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