mirror of
https://github.com/CTCaer/hekate.git
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132 lines
3.4 KiB
C
Executable file
132 lines
3.4 KiB
C
Executable file
/*
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* Copyright (c) 2018 naehrwert
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDMMC_T210_H_
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#define _SDMMC_T210_H_
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#include "types.h"
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#define TEGRA_MMC_PWRCTL_SD_BUS_POWER 0x1
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8 0xA
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0 0xC
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3 0xE
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#define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_MASK 0xF1
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#define TEGRA_MMC_HOSTCTL_1BIT 0x00
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#define TEGRA_MMC_HOSTCTL_4BIT 0x02
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#define TEGRA_MMC_HOSTCTL_8BIT 0x20
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#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE 0x1
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#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE 0x2
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#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE 0x4
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#define TEGRA_MMC_CLKCON_CLKGEN_SELECT 0x20
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL 0x1
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE 0x2
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#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE 0x4
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#define TEGRA_MMC_TRNMOD_DMA_ENABLE 0x1
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#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE 0x2
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#define TEGRA_MMC_TRNMOD_AUTO_CMD12 0x4
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#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE 0x0
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#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ 0x10
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#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT 0x20
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#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK 0x8
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#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK 0x10
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#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER 0x20
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK 0x3
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE 0x0
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 0x1
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 0x2
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#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY 0x3
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#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE 0x1
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#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE 0x2
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#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT 0x8
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#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT 0x8000
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#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT 0x10000
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#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY 0x20
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typedef struct _t210_sdmmc_t
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{
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vu32 sysad;
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vu16 blksize;
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vu16 blkcnt;
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vu32 argument;
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vu16 trnmod;
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vu16 cmdreg;
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vu32 rspreg0;
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vu32 rspreg1;
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vu32 rspreg2;
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vu32 rspreg3;
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vu32 bdata;
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vu32 prnsts;
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vu8 hostctl;
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vu8 pwrcon;
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vu8 blkgap;
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vu8 wakcon;
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vu16 clkcon;
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vu8 timeoutcon;
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vu8 swrst;
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vu16 norintsts;
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vu16 errintsts;
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vu16 norintstsen;
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vu16 errintstsen;
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vu16 norintsigen;
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vu16 errintsigen;
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vu16 acmd12errsts;
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vu16 hostctl2;
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vu32 capareg;
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vu32 capareg_1;
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vu32 maxcurr;
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vu8 res3[4];
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vu16 setacmd12err;
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vu16 setinterr;
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vu8 admaerr;
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vu8 res4[3];
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vu32 admaaddr;
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vu32 admaaddr_hi;
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vu8 res5[156];
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vu16 slotintstatus;
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vu16 hcver;
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vu32 venclkctl;
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vu32 venspictl;
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vu32 venspiintsts;
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vu32 venceatactl;
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vu32 venbootctl;
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vu32 venbootacktout;
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vu32 venbootdattout;
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vu32 vendebouncecnt;
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vu32 venmiscctl;
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vu32 res6[34];
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vu32 field_1AC;
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vu32 field_1B0;
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vu8 res7[8];
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vu32 field_1BC;
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vu32 field_1C0;
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vu32 field_1C4;
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vu8 field_1C8[24];
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vu32 sdmemcmppadctl;
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vu32 autocalcfg;
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vu32 autocalintval;
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vu32 autocalsts;
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vu32 field_1F0;
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} t210_sdmmc_t;
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#endif
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