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218 lines
7 KiB
C
218 lines
7 KiB
C
/*
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* BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
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*
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* Copyright (c) 2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "bpmp.h"
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#include "clock.h"
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#include "t210.h"
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#include "../utils/util.h"
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#define BPMP_CACHE_CONFIG 0x0
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#define CFG_ENABLE (1 << 0)
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#define CFG_FORCE_WRITE_THROUGH (1 << 3)
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#define CFG_DISABLE_WRITE_BUFFER (1 << 10)
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#define CFG_DISABLE_READ_BUFFER (1 << 11)
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#define CFG_FULL_LINE_DIRTY (1 << 13)
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#define CFG_TAG_CHK_ABRT_ON_ERR (1 << 14)
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#define BPMP_CACHE_LOCK 0x4
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#define BPMP_CACHE_SIZE 0xC
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#define BPMP_CACHE_LFSR 0x10
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#define BPMP_CACHE_TAG_STATUS 0x14
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#define BPMP_CACHE_CLKEN_OVERRIDE 0x18
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#define BPMP_CACHE_MAINT_ADDR 0x20
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#define BPMP_CACHE_MAINT_DATA 0x24
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#define BPMP_CACHE_MAINT_REQ 0x28
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#define MAINT_REQ_WAY_BITMAP(x) ((x) << 8)
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#define BPMP_CACHE_INT_MASK 0x40
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#define BPMP_CACHE_INT_CLEAR 0x44
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#define INT_CLR_MAINT_DONE (1 << 0)
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#define BPMP_CACHE_INT_RAW_EVENT 0x48
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#define INT_RAW_EVENT_MAINT_DONE (1 << 0)
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#define BPMP_CACHE_INT_STATUS 0x4C
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#define BPMP_CACHE_RB_CFG 0x80
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#define BPMP_CACHE_WB_CFG 0x84
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#define BPMP_CACHE_MMU_FALLBACK_ENTRY 0xA0
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#define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
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#define BPMP_CACHE_MMU_CFG 0xAC
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#define MMU_CFG_SEQ_EN (1 << 1)
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#define MMU_CFG_TLB_EN (1 << 2)
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#define MMU_CFG_ABORT_STORE_LAST (1 << 4)
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#define BPMP_CACHE_MMU_CMD 0xB0
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#define MMU_CMD_NOP 0
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#define MMU_CMD_INIT 1
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#define MMU_CMD_COPY_SHADOW 2
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#define BPMP_CACHE_MMU_ABORT_STAT 0xB4
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#define BPMP_CACHE_MMU_ABORT_ADDR 0xB8
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#define BPMP_CACHE_MMU_ACTIVE_ENTRIES 0xBC
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#define BPMP_MMU_SHADOW_ENTRY_BASE (BPMP_CACHE_BASE + 0x400)
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#define BPMP_MMU_MAIN_ENTRY_BASE (BPMP_CACHE_BASE + 0x800)
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#define MMU_ENTRY_ADDR_MASK 0xFFFFFFE0
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#define MMU_EN_CACHED (1 << 0)
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#define MMU_EN_EXEC (1 << 1)
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#define MMU_EN_READ (1 << 2)
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#define MMU_EN_WRITE (1 << 3)
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bpmp_mmu_entry_t mmu_entries[] =
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{
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{ 0x80000000, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IPL_LOAD_ADDR, 0x40040000, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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};
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void bpmp_mmu_maintenance(u32 op)
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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return;
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE;
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// This is a blocking operation.
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BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op;
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while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_RAW_EVENT_MAINT_DONE))
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;
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
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}
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
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{
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if (idx > 31)
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return;
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volatile bpmp_mmu_entry_t *mmu_entry = (bpmp_mmu_entry_t *)(BPMP_MMU_SHADOW_ENTRY_BASE + sizeof(bpmp_mmu_entry_t) * idx);
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if (entry->enable)
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{
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mmu_entry->min_addr = entry->min_addr & MMU_ENTRY_ADDR_MASK;
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mmu_entry->max_addr = entry->max_addr & MMU_ENTRY_ADDR_MASK;
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mmu_entry->attr = entry->attr;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
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if (apply)
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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}
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}
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void bpmp_mmu_enable()
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{
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if (BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE)
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return;
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// Init BPMP MMU.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT;
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;
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// Init BPMP MMU entries.
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
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for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
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bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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// Invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = CFG_ENABLE | CFG_FORCE_WRITE_THROUGH | CFG_TAG_CHK_ABRT_ON_ERR;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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}
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void bpmp_mmu_disable()
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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return;
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// Clean and invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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}
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const u8 pllc4_divn[] = {
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0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB.
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85, // BPMP_CLK_LOW_BOOST: 544MHz 33% - 136MHz APB.
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90, // BPMP_CLK_MID_BOOST: 576MHz 41% - 144MHz APB.
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94 // BPMP_CLK_SUPER_BOOST: 602MHz 48% - 150MHz APB.
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//95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB.
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};
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bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
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void bpmp_clk_rate_set(bpmp_freq_t fid)
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{
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if (fid > (BPMP_CLK_MAX - 1))
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fid = BPMP_CLK_MAX - 1;
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if (bpmp_clock_set == fid)
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return;
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if (fid)
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{
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if (bpmp_clock_set)
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{
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// Restore to PLLP source during PLLC4 configuration.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT.
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// Wait a bit for clock source change.
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msleep(10);
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}
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CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = (1 << 30);
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = 4 | (pllc4_divn[fid] << 8) | (1 << 30); // DIVM: 4, DIVP: 1.
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while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & (1 << 27)))
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;
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CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) = (1 << 8) | (1 << 1); // 1.5 div.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_OUT) |= 1; // Get divider out of reset.
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// Wait a bit for PLLC4 to stabilize.
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msleep(10);
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / 4.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3323; // PLLC4_OUT3.
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bpmp_clock_set = fid;
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}
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else
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{
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) =
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(CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888) | 0x3333; // PLLP_OUT.
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// Wait a bit for clock source change.
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msleep(10);
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / 3.
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CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~(1<<30);
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bpmp_clock_set = BPMP_CLK_NORMAL;
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}
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}
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