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The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it. SD Card DDR200 (DDR208) support Proper procedure: 1. Check that Vendor Specific Command System is supported. Used as Enable DDR200 Bus. 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. Access Mode group is left to default 0 (SDR12). 3. Setup clock to 200 or 208 MHz. 4. Set host to DDR bus mode that supports such high clocks. Some hosts have special mode, others use DDR50 and others HS400. 5. Execute Tuning. The true validation that this value in Group 2 activates it, is that DDR50 bus and clocks/timings work fully after that point. On Tegra X1, that can be done with DDR50 host mode. Tuning though can't be done automatically on any DDR mode. So it needs to be done manually and selected tap will be applied from the biggest sampling window. Finally, all that simply works, because the marketing materials for DDR200 are basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode, so sampling on rising and falling edge and with variable output data window. It can be supported by any host that is fast enough to support DDR at 200/208MHz and can do hw/sw tuning for finding the proper sampling window in that mode. Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
174 lines
6 KiB
C
174 lines
6 KiB
C
/*
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* Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved.
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* Copyright (c) 2018-2023 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*/
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#ifndef SD_DEF_H
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#define SD_DEF_H
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/* SD commands type argument response */
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/* class 0 */
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/* This is basically the same command as for MMC with some quirks. */
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#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
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#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
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#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
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/* class 10 */
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#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
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/* class 5 */
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#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
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#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
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/* Application commands */
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#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
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#define SD_APP_SD_STATUS 13 /* adtc R1 */
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#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
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#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
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#define SD_APP_SET_CLR_CARD_DETECT 42 /* adtc R1 */
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#define SD_APP_SEND_SCR 51 /* adtc R1 */
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/* Application secure commands */
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#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */
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#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */
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#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */
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#define SD_APP_SECURE_ERASE 38 /* adtc R1b */
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#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */
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#define SD_APP_GET_MID 44 /* adtc R1 */
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#define SD_APP_SET_CER_RN1 45 /* adtc R1 */
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#define SD_APP_GET_CER_RN2 46 /* adtc R1 */
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#define SD_APP_SET_CER_RES2 47 /* adtc R1 */
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#define SD_APP_GET_CER_RES1 48 /* adtc R1 */
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#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */
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/* OCR bit definitions */
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#define SD_OCR_VDD_18 (1U << 7) /* VDD voltage 1.8 */
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#define SD_VHD_27_36 (1U << 8) /* VDD voltage 2.7 ~ 3.6 */
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#define SD_OCR_VDD_32_33 (1U << 20) /* VDD voltage 3.2 ~ 3.3 */
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#define SD_OCR_S18R (1U << 24) /* 1.8V switching request */
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#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
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#define SD_OCR_XPC (1U << 28) /* SDXC power control */
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#define SD_OCR_CCS (1U << 30) /* Card Capacity Status */
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#define SD_OCR_BUSY (1U << 31) /* Card Power up Status */
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/*
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* SD_SWITCH argument format:
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*
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* [31] Check (0) or switch (1)
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* [30:24] Reserved (0)
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* [23:20] Function group 6
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* [19:16] Function group 5
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* [15:12] Function group 4
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* [11:8] Function group 3
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* [7:4] Function group 2
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* [3:0] Function group 1
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*/
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/*
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* SD_SEND_IF_COND argument format:
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*
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* [31:12] Reserved (0)
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* [11:8] Host Voltage Supply Flags
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* [7:0] Check Pattern (0xAA)
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*/
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/*
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* SD_APP_GET_MKB argument format:
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*
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* [31:24] Number of blocks to read (512 block size)
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* [23:16] MKB ID
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* [15:0] Block offset
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*/
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/*
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* SCR field definitions
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*/
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#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
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#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
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#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
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#define SD_SCR_BUS_WIDTH_1 (1U << 0)
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#define SD_SCR_BUS_WIDTH_4 (1U << 2)
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/*
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* SD bus widths
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*/
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#define SD_BUS_WIDTH_1 0
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#define SD_BUS_WIDTH_4 2
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/*
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* SD bus speeds
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*/
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define HS400_BUS_SPEED 5
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#define SD_MODE_HIGH_SPEED (1U << HIGH_SPEED_BUS_SPEED)
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#define SD_MODE_UHS_SDR12 (1U << UHS_SDR12_BUS_SPEED)
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#define SD_MODE_UHS_SDR25 (1U << UHS_SDR25_BUS_SPEED)
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#define SD_MODE_UHS_SDR50 (1U << UHS_SDR50_BUS_SPEED)
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#define SD_MODE_UHS_SDR104 (1U << UHS_SDR104_BUS_SPEED)
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#define SD_MODE_UHS_DDR50 (1U << UHS_DDR50_BUS_SPEED)
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#define SD_SET_DRIVER_TYPE_B 0
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#define SD_SET_DRIVER_TYPE_A 1
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#define SD_SET_DRIVER_TYPE_C 2
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#define SD_SET_DRIVER_TYPE_D 3
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#define SD_DRIVER_TYPE_B (1U << SD_SET_DRIVER_TYPE_B)
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#define SD_DRIVER_TYPE_A (1U << SD_SET_DRIVER_TYPE_A)
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#define SD_DRIVER_TYPE_C (1U << SD_SET_DRIVER_TYPE_C)
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#define SD_DRIVER_TYPE_D (1U << SD_SET_DRIVER_TYPE_D)
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#define SD_SET_POWER_LIMIT_0_72 0
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#define SD_SET_POWER_LIMIT_1_44 1
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#define SD_SET_POWER_LIMIT_2_16 2
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#define SD_SET_POWER_LIMIT_2_88 3
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#define SD_MAX_POWER_0_72 (1U << SD_SET_POWER_LIMIT_0_72)
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#define SD_MAX_POWER_1_44 (1U << SD_SET_POWER_LIMIT_1_44)
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#define SD_MAX_POWER_2_16 (1U << SD_SET_POWER_LIMIT_2_16)
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#define SD_MAX_POWER_2_88 (1U << SD_SET_POWER_LIMIT_2_88)
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#define SD_SET_CMD_SYSTEM_DEF 0
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#define SD_SET_CMD_SYSTEM_MEC 1
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#define SD_SET_CMD_SYSTEM_OTP 3
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#define SD_SET_CMD_SYSTEM_OSD 3
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#define SD_SET_CMD_SYSTEM_VND 14
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#define UHS_DDR200_BUS_SPEED SD_SET_CMD_SYSTEM_VND
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#define SD_CMD_SYSTEM_DEF (1U << SD_SET_CMD_SYSTEM_DEF)
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#define SD_CMD_SYSTEM_MEC (1U << SD_SET_CMD_SYSTEM_MEC)
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#define SD_CMD_SYSTEM_OTP (1U << SD_SET_CMD_SYSTEM_OTP)
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#define SD_CMD_SYSTEM_OSD (1U << SD_SET_CMD_SYSTEM_OSD)
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#define SD_CMD_SYSTEM_VND (1U << SD_SET_CMD_SYSTEM_VND)
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#define SD_MODE_UHS_DDR200 SD_CMD_SYSTEM_VND
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/*
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* SD_SWITCH mode
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*/
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#define SD_SWITCH_CHECK 0
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#define SD_SWITCH_SET 1
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/*
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* SD_SWITCH function groups
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*/
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#define SD_SWITCH_GRP_ACCESS 0
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#define SD_SWITCH_GRP_CMDSYS 1
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#define SD_SWITCH_GRP_DRVSTR 2
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#define SD_SWITCH_GRP_PWRLIM 3
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/*
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* SD_SWITCH access modes
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*/
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#define SD_SWITCH_ACCESS_DEF 0
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#define SD_SWITCH_ACCESS_HS 1
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#endif /* SD_DEF_H */
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