mirror of
https://github.com/CTCaer/hekate.git
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bafc6f4a1d
- Use always aligned buffers to up the speed for DMA usage. For verification, backup and restore. - Rework verification a little bit and make default Sparse mode. Sparse mode protects from fake sd cards, bad sectors and frequent I/O corruption. Aka, ~100% of cases.
122 lines
2.9 KiB
C
122 lines
2.9 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (C) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "util.h"
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#include "../gfx/di.h"
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#include "../power/max77620.h"
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#include "../rtc/max77620-rtc.h"
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#include "../soc/i2c.h"
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#include "../soc/pmc.h"
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#include "../soc/t210.h"
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extern void sd_unmount();
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u32 get_tmr_s()
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{
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return RTC(APBDEV_RTC_SECONDS);
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}
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u32 get_tmr_ms()
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{
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// The registers must be read with the following order:
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// RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC)
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return (RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10));
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}
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u32 get_tmr_us()
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{
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return TMR(TIMERUS_CNTR_1US); //TIMERUS_CNTR_1US
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}
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void msleep(u32 milliseconds)
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{
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u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10);
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while (((RTC(APBDEV_RTC_MILLI_SECONDS) | (RTC(APBDEV_RTC_SHADOW_SECONDS) << 10)) - start) <= milliseconds)
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;
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}
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void usleep(u32 microseconds)
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{
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u32 start = TMR(TIMERUS_CNTR_1US);
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// Casting to u32 is important!
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while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= microseconds)
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;
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}
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void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops)
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{
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for(u32 i = 0; i < num_ops; i++)
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base[ops[i].off] = ops[i].val;
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}
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void panic(u32 val)
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{
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// Set panic code.
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PMC(APBDEV_PMC_SCRATCH200) = val;
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//PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE;
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TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN;
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TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN;
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TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN;
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TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT;
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while (1)
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;
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}
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void reboot_normal()
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{
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sd_unmount();
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display_end();
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panic(0x21); // Bypass fuse programming in package1.
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}
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void reboot_rcm()
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{
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sd_unmount();
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display_end();
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PMC(APBDEV_PMC_SCRATCH0) = 2; // Reboot into rcm.
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PMC(APBDEV_PMC_CNTRL) |= PMC_CNTRL_MAIN_RST;
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while (true)
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usleep(1);
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}
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void power_off()
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{
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sd_unmount();
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// Stop the alarm, in case we injected and powered off too fast.
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max77620_rtc_stop_alarm();
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//TODO: we should probably make sure all regulators are powered off properly.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF);
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}
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#define CRC32C_POLY 0x82F63B78
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u32 crc32c(const void *buf, u32 len)
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{
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const u8 *cbuf = (const u8 *)buf;
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u32 crc = 0xFFFFFFFF;
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while (len--)
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{
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crc ^= *cbuf++;
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for (int i = 0; i < 8; i++)
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crc = crc & 1 ? (crc >> 1) ^ CRC32C_POLY : crc >> 1;
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}
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return ~crc;
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}
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