2
1
Fork 0
mirror of https://github.com/yuzu-emu/yuzu.git synced 2024-07-04 23:31:19 +01:00
yuzu/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp

244 lines
7.4 KiB
C++
Raw Normal View History

2021-02-08 05:54:35 +00:00
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "shader_recompiler/backend/spirv/emit_spirv.h"
namespace Shader::Backend::SPIRV {
2021-03-29 02:33:52 +01:00
namespace {
void SetZeroFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)};
if (!zero) {
return;
}
zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
zero->Invalidate();
}
void SetSignFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
IR::Inst* const sign{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)};
if (!sign) {
return;
}
sign->SetDefinition(ctx.OpSLessThan(ctx.U1, result, ctx.u32_zero_value));
sign->Invalidate();
}
} // Anonymous namespace
2021-02-08 05:54:35 +00:00
2021-02-17 03:59:28 +00:00
Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
Id result{};
if (IR::Inst* const carry{inst->GetAssociatedPseudoOperation(IR::Opcode::GetCarryFromOp)}) {
const Id carry_type{ctx.TypeStruct(ctx.U32[1], ctx.U32[1])};
const Id carry_result{ctx.OpIAddCarry(carry_type, a, b)};
result = ctx.OpCompositeExtract(ctx.U32[1], carry_result, 0U);
const Id carry_value{ctx.OpCompositeExtract(ctx.U32[1], carry_result, 1U)};
carry->SetDefinition(ctx.OpINotEqual(ctx.U1, carry_value, ctx.u32_zero_value));
carry->Invalidate();
} else {
result = ctx.OpIAdd(ctx.U32[1], a, b);
2021-02-08 05:54:35 +00:00
}
2021-03-29 02:33:52 +01:00
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
if (IR::Inst * overflow{inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
// https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
const Id is_positive{ctx.OpSGreaterThanEqual(ctx.U1, a, ctx.u32_zero_value)};
const Id sub_a{ctx.OpISub(ctx.U32[1], ctx.Constant(ctx.U32[1], s32_max), a)};
const Id positive_test{ctx.OpSGreaterThan(ctx.U1, b, sub_a)};
const Id negative_test{ctx.OpSLessThan(ctx.U1, b, sub_a)};
const Id carry_flag{ctx.OpSelect(ctx.U1, is_positive, positive_test, negative_test)};
overflow->SetDefinition(carry_flag);
overflow->Invalidate();
}
return result;
2021-02-08 05:54:35 +00:00
}
2021-02-17 03:59:28 +00:00
void EmitIAdd64(EmitContext&) {
2021-02-08 05:54:35 +00:00
throw NotImplementedException("SPIR-V Instruction");
}
2021-02-17 03:59:28 +00:00
Id EmitISub32(EmitContext& ctx, Id a, Id b) {
2021-02-16 07:10:22 +00:00
return ctx.OpISub(ctx.U32[1], a, b);
2021-02-08 05:54:35 +00:00
}
2021-02-17 03:59:28 +00:00
void EmitISub64(EmitContext&) {
2021-02-08 05:54:35 +00:00
throw NotImplementedException("SPIR-V Instruction");
}
2021-02-17 03:59:28 +00:00
Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
2021-02-16 07:10:22 +00:00
return ctx.OpIMul(ctx.U32[1], a, b);
2021-02-08 05:54:35 +00:00
}
Id EmitINeg32(EmitContext& ctx, Id value) {
return ctx.OpSNegate(ctx.U32[1], value);
2021-02-08 05:54:35 +00:00
}
2021-03-05 06:15:16 +00:00
Id EmitINeg64(EmitContext& ctx, Id value) {
return ctx.OpSNegate(ctx.U64, value);
}
Id EmitIAbs32(EmitContext& ctx, Id value) {
return ctx.OpSAbs(ctx.U32[1], value);
2021-02-08 05:54:35 +00:00
}
2021-03-20 08:04:12 +00:00
Id EmitIAbs64(EmitContext& ctx, Id value) {
return ctx.OpSAbs(ctx.U64, value);
}
2021-02-17 03:59:28 +00:00
Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
2021-02-16 07:10:22 +00:00
return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
2021-02-08 05:54:35 +00:00
}
2021-03-07 19:48:03 +00:00
Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftLeftLogical(ctx.U64, base, shift);
2021-02-08 05:54:35 +00:00
}
2021-03-07 19:48:03 +00:00
Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftRightLogical(ctx.U32[1], base, shift);
2021-03-05 06:15:16 +00:00
}
2021-03-07 19:48:03 +00:00
Id EmitShiftRightLogical64(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftRightLogical(ctx.U64, base, shift);
}
Id EmitShiftRightArithmetic32(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftRightArithmetic(ctx.U32[1], base, shift);
}
Id EmitShiftRightArithmetic64(EmitContext& ctx, Id base, Id shift) {
return ctx.OpShiftRightArithmetic(ctx.U64, base, shift);
2021-02-08 05:54:35 +00:00
}
2021-04-11 23:16:47 +01:00
Id EmitBitwiseAnd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseAnd(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-02-08 05:54:35 +00:00
}
2021-04-11 23:16:47 +01:00
Id EmitBitwiseOr32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseOr(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-02-08 05:54:35 +00:00
}
2021-04-11 23:16:47 +01:00
Id EmitBitwiseXor32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
const Id result{ctx.OpBitwiseXor(ctx.U32[1], a, b)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-02-08 05:54:35 +00:00
}
Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count) {
return ctx.OpBitFieldInsert(ctx.U32[1], base, insert, offset, count);
2021-02-08 05:54:35 +00:00
}
2021-03-29 02:33:52 +01:00
Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
const Id result{ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-02-08 05:54:35 +00:00
}
2021-03-08 03:01:22 +00:00
Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
2021-03-29 02:33:52 +01:00
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
2021-03-08 03:01:22 +00:00
return result;
2021-02-08 05:54:35 +00:00
}
2021-02-25 05:46:40 +00:00
Id EmitBitReverse32(EmitContext& ctx, Id value) {
return ctx.OpBitReverse(ctx.U32[1], value);
}
2021-02-27 02:41:46 +00:00
Id EmitBitCount32(EmitContext& ctx, Id value) {
return ctx.OpBitCount(ctx.U32[1], value);
}
2021-03-01 20:58:16 +00:00
Id EmitBitwiseNot32(EmitContext& ctx, Id value) {
return ctx.OpNot(ctx.U32[1], value);
}
Id EmitFindSMsb32(EmitContext& ctx, Id value) {
return ctx.OpFindSMsb(ctx.U32[1], value);
}
Id EmitFindUMsb32(EmitContext& ctx, Id value) {
return ctx.OpFindUMsb(ctx.U32[1], value);
2021-02-27 02:41:46 +00:00
}
2021-03-01 04:33:53 +00:00
Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
return ctx.OpSMin(ctx.U32[1], a, b);
}
Id EmitUMin32(EmitContext& ctx, Id a, Id b) {
return ctx.OpUMin(ctx.U32[1], a, b);
}
Id EmitSMax32(EmitContext& ctx, Id a, Id b) {
return ctx.OpSMax(ctx.U32[1], a, b);
}
Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
return ctx.OpUMax(ctx.U32[1], a, b);
}
2021-03-29 02:33:52 +01:00
Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
const Id result{ctx.OpSClamp(ctx.U32[1], value, min, max)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-03-28 04:01:28 +01:00
}
2021-03-29 02:33:52 +01:00
Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
const Id result{ctx.OpUClamp(ctx.U32[1], value, min, max)};
SetZeroFlag(ctx, inst, result);
SetSignFlag(ctx, inst, result);
return result;
2021-03-28 04:01:28 +01:00
}
2021-02-17 03:59:28 +00:00
Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
2021-02-16 07:10:22 +00:00
return ctx.OpSLessThan(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpULessThan(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpIEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitSLessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSLessThanEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitULessThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpULessThanEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
2021-02-17 03:59:28 +00:00
Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
2021-02-16 07:10:22 +00:00
return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitUGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpUGreaterThan(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitINotEqual(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpINotEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
Id EmitSGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
return ctx.OpSGreaterThanEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
2021-02-17 03:59:28 +00:00
Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
2021-02-16 07:10:22 +00:00
return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
2021-02-08 05:54:35 +00:00
}
} // namespace Shader::Backend::SPIRV