2021-04-11 07:07:02 +01:00
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id SharedPointer(EmitContext& ctx, Id offset, u32 index_offset = 0) {
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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if (index_offset > 0) {
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index = ctx.OpIAdd(ctx.U32[1], index, ctx.Constant(ctx.U32[1], index_offset));
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}
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return ctx.profile.support_explicit_workgroup_layout
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? ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, ctx.u32_zero_value, index)
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: ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index);
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}
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Id StorageIndex(EmitContext& ctx, const IR::Value& offset, size_t element_size) {
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if (offset.IsImmediate()) {
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const u32 imm_offset{static_cast<u32>(offset.U32() / element_size)};
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return ctx.Constant(ctx.U32[1], imm_offset);
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}
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const u32 shift{static_cast<u32>(std::countr_zero(element_size))};
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const Id index{ctx.Def(offset)};
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if (shift == 0) {
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return index;
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}
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const Id shift_id{ctx.Constant(ctx.U32[1], shift)};
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return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id);
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}
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Id StoragePointer(EmitContext& ctx, const StorageTypeDefinition& type_def,
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Id StorageDefinitions::*member_ptr, const IR::Value& binding,
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const IR::Value& offset, size_t element_size) {
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if (!binding.IsImmediate()) {
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throw NotImplementedException("Dynamic storage buffer indexing");
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}
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const Id ssbo{ctx.ssbos[binding.U32()].*member_ptr};
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const Id index{StorageIndex(ctx, offset, element_size)};
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return ctx.OpAccessChain(type_def.element, ssbo, ctx.u32_zero_value, index);
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}
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std::pair<Id, Id> AtomicArgs(EmitContext& ctx) {
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const Id scope{ctx.Constant(ctx.U32[1], static_cast<u32>(spv::Scope::Device))};
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const Id semantics{ctx.u32_zero_value};
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return {scope, semantics};
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}
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Id SharedAtomicU32(EmitContext& ctx, Id offset, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const Id pointer{SharedPointer(ctx, offset)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
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}
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Id StorageAtomicU32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id)) {
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const Id pointer{StoragePointer(ctx, ctx.storage_types.U32, &StorageDefinitions::U32, binding,
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offset, sizeof(u32))};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U32[1], pointer, scope, semantics, value);
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}
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Id StorageAtomicU64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, Id value,
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Id (Sirit::Module::*atomic_func)(Id, Id, Id, Id, Id),
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Id (Sirit::Module::*non_atomic_func)(Id, Id, Id)) {
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if (ctx.profile.support_int64_atomics) {
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const Id pointer{StoragePointer(ctx, ctx.storage_types.U64, &StorageDefinitions::U64,
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binding, offset, sizeof(u64))};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return (ctx.*atomic_func)(ctx.U64, pointer, scope, semantics, value);
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}
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// LOG_WARNING(..., "Int64 Atomics not supported, fallback to non-atomic");
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const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2,
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binding, offset, sizeof(u32[2]))};
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const Id original_value{ctx.OpBitcast(ctx.U64, ctx.OpLoad(ctx.U32[2], pointer))};
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const Id result{(ctx.*non_atomic_func)(ctx.U64, value, original_value)};
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ctx.OpStore(pointer, result);
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return original_value;
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}
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} // Anonymous namespace
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Id EmitSharedAtomicIAdd32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitSharedAtomicSMin32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMin);
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}
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Id EmitSharedAtomicUMin32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMin);
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}
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Id EmitSharedAtomicSMax32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicSMax);
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}
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Id EmitSharedAtomicUMax32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitSharedAtomicInc32(EmitContext& ctx, Id offset, Id value) {
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_shared, index, value);
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}
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Id EmitSharedAtomicDec32(EmitContext& ctx, Id offset, Id value) {
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_shared, index, value);
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}
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Id EmitSharedAtomicAnd32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicAnd);
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}
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Id EmitSharedAtomicOr32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicOr);
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}
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Id EmitSharedAtomicXor32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicXor);
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}
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Id EmitSharedAtomicExchange32(EmitContext& ctx, Id offset, Id value) {
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return SharedAtomicU32(ctx, offset, value, &Sirit::Module::OpAtomicExchange);
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}
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Id EmitSharedAtomicExchange64(EmitContext& ctx, Id offset, Id value) {
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if (ctx.profile.support_int64_atomics && ctx.profile.support_explicit_workgroup_layout) {
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const Id shift_id{ctx.Constant(ctx.U32[1], 3U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u64, ctx.shared_memory_u64, ctx.u32_zero_value, index)};
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const auto [scope, semantics]{AtomicArgs(ctx)};
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return ctx.OpAtomicExchange(ctx.U64, pointer, scope, semantics, value);
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}
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// LOG_WARNING("Int64 Atomics not supported, fallback to non-atomic");
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const Id pointer_1{SharedPointer(ctx, offset, 0)};
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const Id pointer_2{SharedPointer(ctx, offset, 1)};
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const Id value_1{ctx.OpLoad(ctx.U32[1], pointer_1)};
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const Id value_2{ctx.OpLoad(ctx.U32[1], pointer_2)};
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const Id new_vector{ctx.OpBitcast(ctx.U32[2], value)};
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ctx.OpStore(pointer_1, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 0U));
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ctx.OpStore(pointer_2, ctx.OpCompositeExtract(ctx.U32[1], new_vector, 1U));
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return ctx.OpBitcast(ctx.U64, ctx.OpCompositeConstruct(ctx.U32[2], value_1, value_2));
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}
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Id EmitStorageAtomicIAdd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicIAdd);
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}
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Id EmitStorageAtomicSMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMin);
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}
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Id EmitStorageAtomicUMin32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMin);
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}
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Id EmitStorageAtomicSMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMax);
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}
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Id EmitStorageAtomicUMax32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMax);
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}
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Id EmitStorageAtomicInc32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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const Id ssbo{ctx.ssbos[binding.U32()].U32};
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const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
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return ctx.OpFunctionCall(ctx.U32[1], ctx.increment_cas_ssbo, base_index, value, ssbo);
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}
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Id EmitStorageAtomicDec32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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const Id ssbo{ctx.ssbos[binding.U32()].U32};
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const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
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return ctx.OpFunctionCall(ctx.U32[1], ctx.decrement_cas_ssbo, base_index, value, ssbo);
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}
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Id EmitStorageAtomicAnd32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicAnd);
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}
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Id EmitStorageAtomicOr32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicOr);
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}
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Id EmitStorageAtomicXor32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicXor);
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}
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Id EmitStorageAtomicExchange32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU32(ctx, binding, offset, value, &Sirit::Module::OpAtomicExchange);
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}
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Id EmitStorageAtomicIAdd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicIAdd,
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&Sirit::Module::OpIAdd);
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}
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Id EmitStorageAtomicSMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMin,
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&Sirit::Module::OpSMin);
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}
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Id EmitStorageAtomicUMin64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMin,
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&Sirit::Module::OpUMin);
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}
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Id EmitStorageAtomicSMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicSMax,
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&Sirit::Module::OpSMax);
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}
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Id EmitStorageAtomicUMax64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicUMax,
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&Sirit::Module::OpUMax);
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}
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Id EmitStorageAtomicAnd64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicAnd,
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&Sirit::Module::OpBitwiseAnd);
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}
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Id EmitStorageAtomicOr64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
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Id value) {
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return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicOr,
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|
&Sirit::Module::OpBitwiseOr);
|
2021-04-11 07:07:02 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicXor64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
return StorageAtomicU64(ctx, binding, offset, value, &Sirit::Module::OpAtomicXor,
|
|
|
|
&Sirit::Module::OpBitwiseXor);
|
2021-04-11 07:07:02 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicExchange64(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
|
|
|
if (ctx.profile.support_int64_atomics) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id pointer{StoragePointer(ctx, ctx.storage_types.U64, &StorageDefinitions::U64,
|
|
|
|
binding, offset, sizeof(u64))};
|
|
|
|
const auto [scope, semantics]{AtomicArgs(ctx)};
|
|
|
|
return ctx.OpAtomicExchange(ctx.U64, pointer, scope, semantics, value);
|
2021-04-11 07:07:02 +01:00
|
|
|
}
|
2021-04-13 09:32:21 +01:00
|
|
|
// LOG_WARNING(..., "Int64 Atomics not supported, fallback to non-atomic");
|
|
|
|
const Id pointer{StoragePointer(ctx, ctx.storage_types.U32x2, &StorageDefinitions::U32x2,
|
|
|
|
binding, offset, sizeof(u32[2]))};
|
|
|
|
const Id original{ctx.OpBitcast(ctx.U64, ctx.OpLoad(ctx.U32[2], pointer))};
|
|
|
|
ctx.OpStore(pointer, value);
|
|
|
|
return original;
|
2021-04-11 07:07:02 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicAddF32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
return ctx.OpFunctionCall(ctx.F32[1], ctx.f32_add_cas, base_index, value, ssbo);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicAddF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_add_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpBitcast(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicAddF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_add_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpPackHalf2x16(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicMinF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_min_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpBitcast(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicMinF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_min_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpPackHalf2x16(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicMaxF16x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F16[2], ctx.f16x2_max_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpBitcast(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitStorageAtomicMaxF32x2(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
|
|
|
|
Id value) {
|
2021-04-13 09:32:21 +01:00
|
|
|
const Id ssbo{ctx.ssbos[binding.U32()].U32};
|
2021-04-11 07:07:02 +01:00
|
|
|
const Id base_index{StorageIndex(ctx, offset, sizeof(u32))};
|
|
|
|
const Id result{ctx.OpFunctionCall(ctx.F32[2], ctx.f32x2_max_cas, base_index, value, ssbo)};
|
|
|
|
return ctx.OpPackHalf2x16(ctx.U32[1], result);
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicIAdd32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicSMin32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicUMin32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicSMax32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicUMax32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicInc32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicDec32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicAnd32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicOr32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicXor32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicExchange32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicIAdd64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicSMin64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicUMin64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicSMax64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicUMax64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicInc64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicDec64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicAnd64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicOr64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicXor64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicExchange64(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicAddF32(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicAddF16x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicAddF32x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicMinF16x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicMinF32x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicMaxF16x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
Id EmitGlobalAtomicMaxF32x2(EmitContext&) {
|
|
|
|
throw NotImplementedException("SPIR-V Instruction");
|
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace Shader::Backend::SPIRV
|