mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
commit
1ccc0457d5
2 changed files with 13 additions and 0 deletions
|
@ -332,6 +332,10 @@ union Instruction {
|
||||||
} ipa;
|
} ipa;
|
||||||
|
|
||||||
union {
|
union {
|
||||||
|
BitField<39, 2, u64> tab5cb8_2;
|
||||||
|
BitField<41, 3, u64> tab5c68_1;
|
||||||
|
BitField<44, 2, u64> tab5c68_0;
|
||||||
|
BitField<47, 1, u64> cc;
|
||||||
BitField<48, 1, u64> negate_b;
|
BitField<48, 1, u64> negate_b;
|
||||||
} fmul;
|
} fmul;
|
||||||
|
|
||||||
|
|
|
@ -1038,6 +1038,15 @@ private:
|
||||||
case OpCode::Id::FMUL_R:
|
case OpCode::Id::FMUL_R:
|
||||||
case OpCode::Id::FMUL_IMM: {
|
case OpCode::Id::FMUL_IMM: {
|
||||||
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
|
// FMUL does not have 'abs' bits and only the second operand has a 'neg' bit.
|
||||||
|
ASSERT_MSG(instr.fmul.tab5cb8_2 == 0, "FMUL tab5cb8_2({}) is not implemented",
|
||||||
|
instr.fmul.tab5cb8_2.Value());
|
||||||
|
ASSERT_MSG(instr.fmul.tab5c68_1 == 0, "FMUL tab5cb8_1({}) is not implemented",
|
||||||
|
instr.fmul.tab5c68_1.Value());
|
||||||
|
ASSERT_MSG(instr.fmul.tab5c68_0 == 1, "FMUL tab5cb8_0({}) is not implemented",
|
||||||
|
instr.fmul.tab5c68_0
|
||||||
|
.Value()); // SMO typical sends 1 here which seems to be the default
|
||||||
|
ASSERT_MSG(instr.fmul.cc == 0, "FMUL cc is not implemented");
|
||||||
|
|
||||||
op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
|
op_b = GetOperandAbsNeg(op_b, false, instr.fmul.negate_b);
|
||||||
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
|
regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1,
|
||||||
instr.alu.saturate_d);
|
instr.alu.saturate_d);
|
||||||
|
|
Loading…
Reference in a new issue