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Merge pull request #170 from MerryMage/feature/dynarmic-update-201802
dynarmic: Update to 41ae12263
This commit is contained in:
commit
205daab50d
5 changed files with 48 additions and 34 deletions
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@ -2,7 +2,7 @@
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set -o pipefail
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export MACOSX_DEPLOYMENT_TARGET=10.9
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export MACOSX_DEPLOYMENT_TARGET=10.12
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export Qt5_DIR=$(brew --prefix)/opt/qt5
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export UNICORNDIR=$(pwd)/externals/unicorn
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2
externals/dynarmic
vendored
2
externals/dynarmic
vendored
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@ -1 +1 @@
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Subproject commit a6d17e6bb0ffd16464b7dae8c1124b0c6a742a15
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Subproject commit 41ae12263da7c6d1ffafec6a5b9095977b42367d
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2
externals/xbyak
vendored
2
externals/xbyak
vendored
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@ -1 +1 @@
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Subproject commit d512551e914737300ba35f3c049d1b40effbe76d
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Subproject commit 2794cde79eb71e86490061cac9622ad0067b8d15
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@ -8,9 +8,12 @@
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#include <dynarmic/A64/config.h>
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/memory.h"
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#include "core/hle/kernel/svc.h"
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#include "core/memory.h"
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using Vector = Dynarmic::A64::Vector;
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class ARM_Dynarmic_Callbacks : public Dynarmic::A64::UserCallbacks {
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public:
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explicit ARM_Dynarmic_Callbacks(ARM_Dynarmic& parent) : parent(parent) {}
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@ -28,6 +31,9 @@ public:
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u64 MemoryRead64(u64 vaddr) override {
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return Memory::Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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return {Memory::Read64(vaddr), Memory::Read64(vaddr + 8)};
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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Memory::Write8(vaddr, value);
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@ -41,6 +47,10 @@ public:
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void MemoryWrite64(u64 vaddr, u64 value) override {
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Memory::Write64(vaddr, value);
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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Memory::Write64(vaddr, value[0]);
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Memory::Write64(vaddr + 8, value[1]);
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}
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void InterpreterFallback(u64 pc, size_t num_instructions) override {
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ARM_Interface::ThreadContext ctx;
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@ -52,12 +62,12 @@ public:
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num_interpreted_instructions += num_instructions;
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception /*exception*/) override {
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ASSERT_MSG(false, "ExceptionRaised(%" PRIx64 ")", pc);
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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ASSERT_MSG(false, "ExceptionRaised(exception = %zu, pc = %" PRIx64 ")",
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static_cast<size_t>(exception), pc);
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}
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void CallSVC(u32 swi) override {
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printf("svc %x\n", swi);
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Kernel::CallSVC(swi);
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}
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@ -78,9 +88,13 @@ public:
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u64 tpidrr0_el0 = 0;
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};
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std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_Callbacks>& cb) {
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Dynarmic::A64::UserConfig config{cb.get()};
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return std::make_unique<Dynarmic::A64::Jit>(config);
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}
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ARM_Dynarmic::ARM_Dynarmic()
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: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)),
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jit(Dynarmic::A64::UserConfig{cb.get()}) {
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: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), jit(MakeJit(cb)) {
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ARM_Interface::ThreadContext ctx;
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inner_unicorn.SaveContext(ctx);
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LoadContext(ctx);
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@ -94,27 +108,27 @@ void ARM_Dynarmic::MapBackingMemory(u64 address, size_t size, u8* memory,
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}
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void ARM_Dynarmic::SetPC(u64 pc) {
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jit.SetPC(pc);
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jit->SetPC(pc);
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}
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u64 ARM_Dynarmic::GetPC() const {
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return jit.GetPC();
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return jit->GetPC();
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}
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u64 ARM_Dynarmic::GetReg(int index) const {
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return jit.GetRegister(index);
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return jit->GetRegister(index);
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}
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void ARM_Dynarmic::SetReg(int index, u64 value) {
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jit.SetRegister(index, value);
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jit->SetRegister(index, value);
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}
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u128 ARM_Dynarmic::GetExtReg(int index) const {
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return jit.GetVector(index);
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return jit->GetVector(index);
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}
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void ARM_Dynarmic::SetExtReg(int index, u128 value) {
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jit.SetVector(index, value);
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jit->SetVector(index, value);
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}
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u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const {
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@ -127,11 +141,11 @@ void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
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}
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u32 ARM_Dynarmic::GetCPSR() const {
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return jit.GetPstate();
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return jit->GetPstate();
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}
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void ARM_Dynarmic::SetCPSR(u32 cpsr) {
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jit.SetPstate(cpsr);
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jit->SetPstate(cpsr);
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}
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u64 ARM_Dynarmic::GetTlsAddress() const {
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@ -144,41 +158,41 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
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void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
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cb->ticks_remaining = num_instructions;
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jit.Run();
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jit->Run();
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CoreTiming::AddTicks(num_instructions - cb->num_interpreted_instructions);
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cb->num_interpreted_instructions = 0;
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}
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void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
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ctx.cpu_registers = jit.GetRegisters();
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ctx.sp = jit.GetSP();
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ctx.pc = jit.GetPC();
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ctx.cpsr = jit.GetPstate();
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ctx.fpu_registers = jit.GetVectors();
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ctx.fpscr = jit.GetFpcr();
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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ctx.pc = jit->GetPC();
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ctx.cpsr = jit->GetPstate();
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ctx.fpu_registers = jit->GetVectors();
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ctx.fpscr = jit->GetFpcr();
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ctx.tls_address = cb->tpidrr0_el0;
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}
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void ARM_Dynarmic::LoadContext(const ARM_Interface::ThreadContext& ctx) {
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jit.SetRegisters(ctx.cpu_registers);
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jit.SetSP(ctx.sp);
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jit.SetPC(ctx.pc);
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jit.SetPstate(static_cast<u32>(ctx.cpsr));
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jit.SetVectors(ctx.fpu_registers);
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jit.SetFpcr(static_cast<u32>(ctx.fpscr));
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jit->SetRegisters(ctx.cpu_registers);
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jit->SetSP(ctx.sp);
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jit->SetPC(ctx.pc);
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jit->SetPstate(static_cast<u32>(ctx.cpsr));
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jit->SetVectors(ctx.fpu_registers);
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jit->SetFpcr(static_cast<u32>(ctx.fpscr));
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cb->tpidrr0_el0 = ctx.tls_address;
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}
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void ARM_Dynarmic::PrepareReschedule() {
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if (jit.IsExecuting()) {
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jit.HaltExecution();
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if (jit->IsExecuting()) {
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jit->HaltExecution();
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}
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}
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void ARM_Dynarmic::ClearInstructionCache() {
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jit.ClearCache();
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jit->ClearCache();
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}
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void ARM_Dynarmic::PageTableChanged() {
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UNIMPLEMENTED();
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jit = MakeJit(cb);
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}
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@ -45,6 +45,6 @@ public:
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private:
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friend class ARM_Dynarmic_Callbacks;
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std::unique_ptr<ARM_Dynarmic_Callbacks> cb;
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Dynarmic::A64::Jit jit;
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std::unique_ptr<Dynarmic::A64::Jit> jit;
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ARM_Unicorn inner_unicorn;
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};
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