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https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
Handle RZ cases evaluating the expression instead of the register value.
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parent
7e72b5e453
commit
946777601b
1 changed files with 22 additions and 14 deletions
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@ -347,6 +347,15 @@ public:
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BuildInputList();
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BuildInputList();
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}
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}
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void SetConditionalCodesFromExpression(const std::string& expresion) {
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SetInternalFlag(InternalFlag::ZeroFlag, "(" + expresion + ") == 0");
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete.");
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}
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void SetConditionalCodesFromRegister(const Register& reg, u64 dest_elem = 0) {
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SetConditionalCodesFromExpression(GetRegister(reg, static_cast<u32>(dest_elem)));
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}
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/**
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/**
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* Returns code that does an integer size conversion for the specified size.
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* Returns code that does an integer size conversion for the specified size.
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* @param value Value to perform integer size conversion on.
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* @param value Value to perform integer size conversion on.
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@ -411,10 +420,11 @@ public:
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SetRegister(reg, elem, is_saturated ? "clamp(" + value + ", 0.0, 1.0)" : value,
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SetRegister(reg, elem, is_saturated ? "clamp(" + value + ", 0.0, 1.0)" : value,
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dest_num_components, value_num_components, dest_elem, precise);
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dest_num_components, value_num_components, dest_elem, precise);
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if (sets_cc) {
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if (sets_cc) {
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const std::string zero_condition =
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if (reg == Register::ZeroIndex) {
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"( " + GetRegister(reg, static_cast<u32>(dest_elem)) + " == 0 )";
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SetConditionalCodesFromExpression(value);
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SetInternalFlag(InternalFlag::ZeroFlag, zero_condition);
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} else {
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete.");
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SetConditionalCodesFromRegister(reg, dest_elem);
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}
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}
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}
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}
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}
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@ -442,10 +452,11 @@ public:
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dest_num_components, value_num_components, dest_elem, false);
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dest_num_components, value_num_components, dest_elem, false);
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if (sets_cc) {
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if (sets_cc) {
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const std::string zero_condition =
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if (reg == Register::ZeroIndex) {
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"( " + GetRegister(reg, static_cast<u32>(dest_elem)) + " == 0 )";
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SetConditionalCodesFromExpression(value);
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SetInternalFlag(InternalFlag::ZeroFlag, zero_condition);
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} else {
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LOG_WARNING(HW_GPU, "Condition codes implementation is incomplete.");
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SetConditionalCodesFromRegister(reg, dest_elem);
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}
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}
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}
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}
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}
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@ -3365,14 +3376,11 @@ private:
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") " + combiner + " (" + second_pred + "))";
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") " + combiner + " (" + second_pred + "))";
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if (instr.fset.bf) {
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if (instr.fset.bf) {
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regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1);
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regs.SetRegisterToFloat(instr.gpr0, 0, predicate + " ? 1.0 : 0.0", 1, 1, false,
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instr.generates_cc);
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} else {
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} else {
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regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1,
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regs.SetRegisterToInteger(instr.gpr0, false, 0, predicate + " ? 0xFFFFFFFF : 0", 1,
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1);
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1, false, instr.generates_cc);
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}
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if (instr.generates_cc.Value() != 0) {
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regs.SetInternalFlag(InternalFlag::ZeroFlag, predicate);
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LOG_WARNING(HW_GPU, "FSET Condition Code is incomplete");
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}
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}
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break;
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break;
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}
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}
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