mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
Shader_Ir: Correct TLD4S encoding and implement f16 flag.
This commit is contained in:
parent
84a158c977
commit
af89723fa3
3 changed files with 15 additions and 11 deletions
|
@ -1292,6 +1292,7 @@ union Instruction {
|
||||||
BitField<50, 1, u64> dc_flag;
|
BitField<50, 1, u64> dc_flag;
|
||||||
BitField<51, 1, u64> aoffi_flag;
|
BitField<51, 1, u64> aoffi_flag;
|
||||||
BitField<52, 2, u64> component;
|
BitField<52, 2, u64> component;
|
||||||
|
BitField<55, 1, u64> fp16_flag;
|
||||||
|
|
||||||
bool UsesMiscMode(TextureMiscMode mode) const {
|
bool UsesMiscMode(TextureMiscMode mode) const {
|
||||||
switch (mode) {
|
switch (mode) {
|
||||||
|
@ -1972,7 +1973,7 @@ private:
|
||||||
INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"),
|
INST("1101-01---------", Id::TLDS, Type::Texture, "TLDS"),
|
||||||
INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
|
INST("110010----111---", Id::TLD4, Type::Texture, "TLD4"),
|
||||||
INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"),
|
INST("1101111011111---", Id::TLD4_B, Type::Texture, "TLD4_B"),
|
||||||
INST("1101111100------", Id::TLD4S, Type::Texture, "TLD4S"),
|
INST("11011111--00----", Id::TLD4S, Type::Texture, "TLD4S"),
|
||||||
INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
|
INST("110111110110----", Id::TMML_B, Type::Texture, "TMML_B"),
|
||||||
INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
|
INST("1101111101011---", Id::TMML, Type::Texture, "TMML"),
|
||||||
INST("11011110011110--", Id::TXD_B, Type::Texture, "TXD_B"),
|
INST("11011110011110--", Id::TXD_B, Type::Texture, "TXD_B"),
|
||||||
|
|
|
@ -138,7 +138,11 @@ u32 ShaderIR::DecodeTexture(NodeBlock& bb, u32 pc) {
|
||||||
values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
|
values[element] = Operation(OperationCode::TextureGather, meta, std::move(coords_copy));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (instr.tld4s.fp16_flag) {
|
||||||
|
WriteTexsInstructionHalfFloat(bb, instr, values, true);
|
||||||
|
} else {
|
||||||
WriteTexsInstructionFloat(bb, instr, values, true);
|
WriteTexsInstructionFloat(bb, instr, values, true);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case OpCode::Id::TXD_B:
|
case OpCode::Id::TXD_B:
|
||||||
|
@ -435,14 +439,14 @@ void ShaderIR::WriteTexsInstructionFloat(NodeBlock& bb, Instruction instr, const
|
||||||
}
|
}
|
||||||
|
|
||||||
void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
|
void ShaderIR::WriteTexsInstructionHalfFloat(NodeBlock& bb, Instruction instr,
|
||||||
const Node4& components) {
|
const Node4& components, bool ignore_mask) {
|
||||||
// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
|
// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
|
||||||
// float instruction).
|
// float instruction).
|
||||||
|
|
||||||
Node4 values;
|
Node4 values;
|
||||||
u32 dest_elem = 0;
|
u32 dest_elem = 0;
|
||||||
for (u32 component = 0; component < 4; ++component) {
|
for (u32 component = 0; component < 4; ++component) {
|
||||||
if (!instr.texs.IsComponentEnabled(component))
|
if (!instr.texs.IsComponentEnabled(component) && !ignore_mask)
|
||||||
continue;
|
continue;
|
||||||
values[dest_elem++] = components[component];
|
values[dest_elem++] = components[component];
|
||||||
}
|
}
|
||||||
|
@ -525,7 +529,6 @@ Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
for (u32 element = 0; element < values.size(); ++element) {
|
for (u32 element = 0; element < values.size(); ++element) {
|
||||||
auto copy_coords = coords;
|
auto copy_coords = coords;
|
||||||
MetaTexture meta{*sampler, array, depth_compare, aoffi, {}, bias, lod, {}, element};
|
MetaTexture meta{*sampler, array, depth_compare, aoffi, {}, bias, lod, {}, element};
|
||||||
|
|
|
@ -338,7 +338,7 @@ private:
|
||||||
void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
void WriteTexsInstructionFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
||||||
const Node4& components, bool ignore_mask = false);
|
const Node4& components, bool ignore_mask = false);
|
||||||
void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
void WriteTexsInstructionHalfFloat(NodeBlock& bb, Tegra::Shader::Instruction instr,
|
||||||
const Node4& components);
|
const Node4& components, bool ignore_mask = false);
|
||||||
|
|
||||||
Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
Node4 GetTexCode(Tegra::Shader::Instruction instr, Tegra::Shader::TextureType texture_type,
|
||||||
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
Tegra::Shader::TextureProcessMode process_mode, bool depth_compare,
|
||||||
|
|
Loading…
Reference in a new issue