mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
arm_interface: Remove ARM11-isms from the CPU interface
This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
This commit is contained in:
Lioncash
parent
a94b623dfb
commit
b51e7e0288
7 changed files with 88 additions and 101 deletions
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@ -10,7 +10,7 @@
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namespace Core {
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/// Generic ARM11 CPU interface
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/// Generic ARMv8 CPU interface
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class ARM_Interface : NonCopyable {
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public:
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virtual ~ARM_Interface() {}
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@ -19,9 +19,9 @@ public:
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std::array<u64, 31> cpu_registers;
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u64 sp;
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u64 pc;
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u64 cpsr;
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std::array<u128, 32> fpu_registers;
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u64 fpscr;
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u64 pstate;
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std::array<u128, 32> vector_registers;
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u64 fpcr;
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};
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/// Runs the CPU until an event happens
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@ -69,42 +69,50 @@ public:
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*/
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virtual void SetReg(int index, u64 value) = 0;
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virtual u128 GetExtReg(int index) const = 0;
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virtual void SetExtReg(int index, u128 value) = 0;
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/**
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* Gets the value of a specified vector register.
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*
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* @param index The index of the vector register.
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* @return the value within the vector register.
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*/
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virtual u128 GetVectorReg(int index) const = 0;
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/**
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* Gets the value of a VFP register
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* @param index Register index (0-31)
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* @return Returns the value in the register
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* Sets a given value into a vector register.
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*
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* @param index The index of the vector register.
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* @param value The new value to place in the register.
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*/
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virtual u32 GetVFPReg(int index) const = 0;
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virtual void SetVectorReg(int index, u128 value) = 0;
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/**
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* Sets a VFP register to the given value
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* @param index Register index (0-31)
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* @param value Value to set register to
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* Get the current PSTATE register
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* @return Returns the value of the PSTATE register
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*/
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virtual void SetVFPReg(int index, u32 value) = 0;
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virtual u32 GetPSTATE() const = 0;
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/**
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* Get the current CPSR register
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* @return Returns the value of the CPSR register
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* Set the current PSTATE register
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* @param pstate Value to set PSTATE to
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*/
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virtual u32 GetCPSR() const = 0;
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/**
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* Set the current CPSR register
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* @param cpsr Value to set CPSR to
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*/
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virtual void SetCPSR(u32 cpsr) = 0;
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virtual void SetPSTATE(u32 pstate) = 0;
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virtual VAddr GetTlsAddress() const = 0;
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virtual void SetTlsAddress(VAddr address) = 0;
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/**
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* Gets the value within the TPIDR_EL0 (read/write software thread ID) register.
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*
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* @return the value within the register.
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*/
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virtual u64 GetTPIDR_EL0() const = 0;
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/**
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* Sets a new value within the TPIDR_EL0 (read/write software thread ID) register.
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*
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* @param value The new value to place in the register.
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*/
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virtual void SetTPIDR_EL0(u64 value) = 0;
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/**
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@ -119,6 +127,7 @@ public:
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*/
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virtual void LoadContext(const ThreadContext& ctx) = 0;
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/// Clears the exclusive monitor's state.
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virtual void ClearExclusiveState() = 0;
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/// Prepare core for thread reschedule (if needed to correctly handle state)
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@ -194,29 +194,20 @@ void ARM_Dynarmic::SetReg(int index, u64 value) {
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jit->SetRegister(index, value);
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}
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u128 ARM_Dynarmic::GetExtReg(int index) const {
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u128 ARM_Dynarmic::GetVectorReg(int index) const {
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return jit->GetVector(index);
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}
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void ARM_Dynarmic::SetExtReg(int index, u128 value) {
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void ARM_Dynarmic::SetVectorReg(int index, u128 value) {
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jit->SetVector(index, value);
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}
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u32 ARM_Dynarmic::GetVFPReg(int /*index*/) const {
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UNIMPLEMENTED();
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return {};
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}
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void ARM_Dynarmic::SetVFPReg(int /*index*/, u32 /*value*/) {
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UNIMPLEMENTED();
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}
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u32 ARM_Dynarmic::GetCPSR() const {
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u32 ARM_Dynarmic::GetPSTATE() const {
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return jit->GetPstate();
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}
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void ARM_Dynarmic::SetCPSR(u32 cpsr) {
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jit->SetPstate(cpsr);
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void ARM_Dynarmic::SetPSTATE(u32 pstate) {
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jit->SetPstate(pstate);
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}
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u64 ARM_Dynarmic::GetTlsAddress() const {
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@ -239,18 +230,18 @@ void ARM_Dynarmic::SaveContext(ThreadContext& ctx) {
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ctx.cpu_registers = jit->GetRegisters();
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ctx.sp = jit->GetSP();
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ctx.pc = jit->GetPC();
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ctx.cpsr = jit->GetPstate();
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ctx.fpu_registers = jit->GetVectors();
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ctx.fpscr = jit->GetFpcr();
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ctx.pstate = jit->GetPstate();
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ctx.vector_registers = jit->GetVectors();
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ctx.fpcr = jit->GetFpcr();
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}
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void ARM_Dynarmic::LoadContext(const ThreadContext& ctx) {
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jit->SetRegisters(ctx.cpu_registers);
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jit->SetSP(ctx.sp);
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jit->SetPC(ctx.pc);
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jit->SetPstate(static_cast<u32>(ctx.cpsr));
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jit->SetVectors(ctx.fpu_registers);
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jit->SetFpcr(static_cast<u32>(ctx.fpscr));
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jit->SetPstate(static_cast<u32>(ctx.pstate));
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jit->SetVectors(ctx.vector_registers);
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jit->SetFpcr(static_cast<u32>(ctx.fpcr));
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}
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void ARM_Dynarmic::PrepareReschedule() {
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@ -29,14 +29,12 @@ public:
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u64 GetPC() const override;
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u64 GetReg(int index) const override;
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void SetReg(int index, u64 value) override;
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u128 GetExtReg(int index) const override;
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void SetExtReg(int index, u128 value) override;
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u32 GetVFPReg(int index) const override;
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void SetVFPReg(int index, u32 value) override;
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u32 GetCPSR() const override;
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u128 GetVectorReg(int index) const override;
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void SetVectorReg(int index, u128 value) override;
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u32 GetPSTATE() const override;
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void SetPSTATE(u32 pstate) override;
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void Run() override;
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void Step() override;
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void SetCPSR(u32 cpsr) override;
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VAddr GetTlsAddress() const override;
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void SetTlsAddress(VAddr address) override;
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void SetTPIDR_EL0(u64 value) override;
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@ -131,33 +131,24 @@ void ARM_Unicorn::SetReg(int regn, u64 val) {
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CHECKED(uc_reg_write(uc, treg, &val));
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}
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u128 ARM_Unicorn::GetExtReg(int /*index*/) const {
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u128 ARM_Unicorn::GetVectorReg(int /*index*/) const {
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UNIMPLEMENTED();
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static constexpr u128 res{};
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return res;
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}
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void ARM_Unicorn::SetExtReg(int /*index*/, u128 /*value*/) {
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void ARM_Unicorn::SetVectorReg(int /*index*/, u128 /*value*/) {
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UNIMPLEMENTED();
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}
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u32 ARM_Unicorn::GetVFPReg(int /*index*/) const {
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UNIMPLEMENTED();
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return {};
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}
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void ARM_Unicorn::SetVFPReg(int /*index*/, u32 /*value*/) {
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UNIMPLEMENTED();
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}
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u32 ARM_Unicorn::GetCPSR() const {
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u32 ARM_Unicorn::GetPSTATE() const {
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u64 nzcv{};
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &nzcv));
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return static_cast<u32>(nzcv);
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}
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void ARM_Unicorn::SetCPSR(u32 cpsr) {
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u64 nzcv = cpsr;
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void ARM_Unicorn::SetPSTATE(u32 pstate) {
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u64 nzcv = pstate;
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &nzcv));
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}
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@ -219,7 +210,7 @@ void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_SP, &ctx.sp));
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_PC, &ctx.pc));
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
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CHECKED(uc_reg_read(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
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for (auto i = 0; i < 29; ++i) {
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uregs[i] = UC_ARM64_REG_X0 + i;
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@ -234,7 +225,7 @@ void ARM_Unicorn::SaveContext(ThreadContext& ctx) {
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for (int i = 0; i < 32; ++i) {
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uregs[i] = UC_ARM64_REG_Q0 + i;
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tregs[i] = &ctx.fpu_registers[i];
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tregs[i] = &ctx.vector_registers[i];
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}
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CHECKED(uc_reg_read_batch(uc, uregs, tregs, 32));
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@ -246,7 +237,7 @@ void ARM_Unicorn::LoadContext(const ThreadContext& ctx) {
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_SP, &ctx.sp));
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_PC, &ctx.pc));
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.cpsr));
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CHECKED(uc_reg_write(uc, UC_ARM64_REG_NZCV, &ctx.pstate));
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for (int i = 0; i < 29; ++i) {
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uregs[i] = UC_ARM64_REG_X0 + i;
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@ -261,7 +252,7 @@ void ARM_Unicorn::LoadContext(const ThreadContext& ctx) {
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for (auto i = 0; i < 32; ++i) {
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uregs[i] = UC_ARM64_REG_Q0 + i;
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tregs[i] = (void*)&ctx.fpu_registers[i];
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tregs[i] = (void*)&ctx.vector_registers[i];
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}
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CHECKED(uc_reg_write_batch(uc, uregs, tregs, 32));
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@ -22,12 +22,10 @@ public:
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u64 GetPC() const override;
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u64 GetReg(int index) const override;
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void SetReg(int index, u64 value) override;
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u128 GetExtReg(int index) const override;
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void SetExtReg(int index, u128 value) override;
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u32 GetVFPReg(int index) const override;
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void SetVFPReg(int index, u32 value) override;
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u32 GetCPSR() const override;
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void SetCPSR(u32 cpsr) override;
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u128 GetVectorReg(int index) const override;
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void SetVectorReg(int index, u128 value) override;
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u32 GetPSTATE() const override;
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void SetPSTATE(u32 pstate) override;
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VAddr GetTlsAddress() const override;
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void SetTlsAddress(VAddr address) override;
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void SetTPIDR_EL0(u64 value) override;
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@ -65,9 +65,9 @@ constexpr u32 MSG_WAITALL = 8;
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constexpr u32 LR_REGISTER = 30;
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constexpr u32 SP_REGISTER = 31;
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constexpr u32 PC_REGISTER = 32;
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constexpr u32 CPSR_REGISTER = 33;
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constexpr u32 PSTATE_REGISTER = 33;
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constexpr u32 UC_ARM64_REG_Q0 = 34;
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constexpr u32 FPSCR_REGISTER = 66;
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constexpr u32 FPCR_REGISTER = 66;
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// TODO/WiP - Used while working on support for FPU
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constexpr u32 TODO_DUMMY_REG_997 = 997;
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@ -116,7 +116,7 @@ constexpr char target_xml[] =
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<reg name="pc" bitsize="64" type="code_ptr"/>
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<flags id="cpsr_flags" size="4">
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<flags id="pstate_flags" size="4">
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<field name="SP" start="0" end="0"/>
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<field name="" start="1" end="1"/>
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<field name="EL" start="2" end="3"/>
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@ -135,7 +135,7 @@ constexpr char target_xml[] =
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<field name="Z" start="30" end="30"/>
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<field name="N" start="31" end="31"/>
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</flags>
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<reg name="cpsr" bitsize="32" type="cpsr_flags"/>
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<reg name="pstate" bitsize="32" type="pstate_flags"/>
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</feature>
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<feature name="org.gnu.gdb.aarch64.fpu">
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</feature>
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@ -227,10 +227,10 @@ static u64 RegRead(std::size_t id, Kernel::Thread* thread = nullptr) {
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return thread->context.sp;
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} else if (id == PC_REGISTER) {
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return thread->context.pc;
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} else if (id == CPSR_REGISTER) {
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return thread->context.cpsr;
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} else if (id > CPSR_REGISTER && id < FPSCR_REGISTER) {
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return thread->context.fpu_registers[id - UC_ARM64_REG_Q0][0];
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} else if (id == PSTATE_REGISTER) {
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return thread->context.pstate;
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} else if (id > PSTATE_REGISTER && id < FPCR_REGISTER) {
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return thread->context.vector_registers[id - UC_ARM64_REG_Q0][0];
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} else {
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return 0;
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}
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@ -247,10 +247,10 @@ static void RegWrite(std::size_t id, u64 val, Kernel::Thread* thread = nullptr)
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thread->context.sp = val;
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} else if (id == PC_REGISTER) {
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thread->context.pc = val;
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} else if (id == CPSR_REGISTER) {
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thread->context.cpsr = val;
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} else if (id > CPSR_REGISTER && id < FPSCR_REGISTER) {
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thread->context.fpu_registers[id - (CPSR_REGISTER + 1)][0] = val;
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} else if (id == PSTATE_REGISTER) {
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thread->context.pstate = val;
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} else if (id > PSTATE_REGISTER && id < FPCR_REGISTER) {
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thread->context.vector_registers[id - (PSTATE_REGISTER + 1)][0] = val;
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}
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}
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@ -781,11 +781,11 @@ static void ReadRegister() {
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LongToGdbHex(reply, RegRead(id, current_thread));
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} else if (id == PC_REGISTER) {
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LongToGdbHex(reply, RegRead(id, current_thread));
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} else if (id == CPSR_REGISTER) {
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IntToGdbHex(reply, (u32)RegRead(id, current_thread));
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} else if (id >= UC_ARM64_REG_Q0 && id < FPSCR_REGISTER) {
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} else if (id == PSTATE_REGISTER) {
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IntToGdbHex(reply, static_cast<u32>(RegRead(id, current_thread)));
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} else if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
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LongToGdbHex(reply, RegRead(id, current_thread));
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} else if (id == FPSCR_REGISTER) {
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} else if (id == FPCR_REGISTER) {
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LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_998, current_thread));
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} else {
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LongToGdbHex(reply, RegRead(TODO_DUMMY_REG_997, current_thread));
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@ -811,7 +811,7 @@ static void ReadRegisters() {
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bufptr += 16;
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IntToGdbHex(bufptr, (u32)RegRead(CPSR_REGISTER, current_thread));
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IntToGdbHex(bufptr, static_cast<u32>(RegRead(PSTATE_REGISTER, current_thread)));
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bufptr += 8;
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@ -843,11 +843,11 @@ static void WriteRegister() {
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RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
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} else if (id == PC_REGISTER) {
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RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
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} else if (id == CPSR_REGISTER) {
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} else if (id == PSTATE_REGISTER) {
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RegWrite(id, GdbHexToInt(buffer_ptr), current_thread);
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} else if (id >= UC_ARM64_REG_Q0 && id < FPSCR_REGISTER) {
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} else if (id >= UC_ARM64_REG_Q0 && id < FPCR_REGISTER) {
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RegWrite(id, GdbHexToLong(buffer_ptr), current_thread);
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} else if (id == FPSCR_REGISTER) {
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} else if (id == FPCR_REGISTER) {
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RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr), current_thread);
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} else {
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RegWrite(TODO_DUMMY_REG_997, GdbHexToLong(buffer_ptr), current_thread);
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@ -866,16 +866,16 @@ static void WriteRegisters() {
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if (command_buffer[0] != 'G')
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return SendReply("E01");
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for (u32 i = 0, reg = 0; reg <= FPSCR_REGISTER; i++, reg++) {
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for (u32 i = 0, reg = 0; reg <= FPCR_REGISTER; i++, reg++) {
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if (reg <= SP_REGISTER) {
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RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread);
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} else if (reg == PC_REGISTER) {
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RegWrite(PC_REGISTER, GdbHexToLong(buffer_ptr + i * 16), current_thread);
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} else if (reg == CPSR_REGISTER) {
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RegWrite(CPSR_REGISTER, GdbHexToInt(buffer_ptr + i * 16), current_thread);
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} else if (reg >= UC_ARM64_REG_Q0 && reg < FPSCR_REGISTER) {
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} else if (reg == PSTATE_REGISTER) {
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RegWrite(PSTATE_REGISTER, GdbHexToInt(buffer_ptr + i * 16), current_thread);
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} else if (reg >= UC_ARM64_REG_Q0 && reg < FPCR_REGISTER) {
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RegWrite(reg, GdbHexToLong(buffer_ptr + i * 16), current_thread);
|
||||
} else if (reg == FPSCR_REGISTER) {
|
||||
} else if (reg == FPCR_REGISTER) {
|
||||
RegWrite(TODO_DUMMY_REG_998, GdbHexToLong(buffer_ptr + i * 16), current_thread);
|
||||
} else {
|
||||
UNIMPLEMENTED();
|
||||
|
|
|
|||
|
|
@ -217,8 +217,8 @@ static void ResetThreadContext(Core::ARM_Interface::ThreadContext& context, VAdd
|
|||
context.cpu_registers[0] = arg;
|
||||
context.pc = entry_point;
|
||||
context.sp = stack_top;
|
||||
context.cpsr = 0;
|
||||
context.fpscr = 0;
|
||||
context.pstate = 0;
|
||||
context.fpcr = 0;
|
||||
}
|
||||
|
||||
ResultVal<SharedPtr<Thread>> Thread::Create(KernelCore& kernel, std::string name, VAddr entry_point,
|
||||
|
|
|
|||
Loading…
Reference in a new issue