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Code Issues Releases Activity

texture_cache: Implement guest flushing

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This commit is contained in:
Fernando Sahmkow 2019-05-08 10:32:30 -04:00 committed by ReinUsesLisp
parent de0b1cb2b2
commit ba677ccb5a
3 changed files with 29 additions and 10 deletions
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4
src/video_core/renderer_opengl/gl_rasterizer.cpp
View file

@ -722,7 +722,7 @@ void RasterizerOpenGL::FlushRegion(CacheAddr addr, u64 size) {
if (!addr || !size) {
return;
}
// texture_cache.FlushRegion(addr, size);
texture_cache.FlushRegion(addr, size);
global_cache.FlushRegion(addr, size);
}
@ -738,7 +738,9 @@ void RasterizerOpenGL::InvalidateRegion(CacheAddr addr, u64 size) {
}
void RasterizerOpenGL::FlushAndInvalidateRegion(CacheAddr addr, u64 size) {
if (Settings::values.use_accurate_gpu_emulation) {
FlushRegion(addr, size);
}
InvalidateRegion(addr, size);
}

19
src/video_core/texture_cache/surface_base.cpp
View file

@ -63,6 +63,9 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
std::vector<u8>& staging_buffer) {
MICROPROFILE_SCOPE(GPU_Load_Texture);
const auto host_ptr{memory_manager.GetPointer(gpu_addr)};
if (!host_ptr) {
return;
}
if (params.is_tiled) {
ASSERT_MSG(params.block_width == 1, "Block width is defined as {} on texture target {}",
params.block_width, static_cast<u32>(params.target));
@ -103,7 +106,10 @@ void SurfaceBaseImpl::LoadBuffer(Tegra::MemoryManager& memory_manager,
void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
std::vector<u8>& staging_buffer) {
MICROPROFILE_SCOPE(GPU_Flush_Texture);
auto host_ptr = memory_manager.GetPointer(gpu_addr);
const auto host_ptr{memory_manager.GetPointer(gpu_addr)};
if (!host_ptr) {
return;
}
if (params.is_tiled) {
ASSERT_MSG(params.block_width == 1, "Block width is defined as {}", params.block_width);
for (u32 level = 0; level < params.num_levels; ++level) {
@ -112,25 +118,22 @@ void SurfaceBaseImpl::FlushBuffer(Tegra::MemoryManager& memory_manager,
staging_buffer.data() + host_offset, level);
}
} else {
UNIMPLEMENTED();
/*
ASSERT(params.target == SurfaceTarget::Texture2D);
ASSERT(params.num_levels == 1);
const u32 bpp{params.GetFormatBpp() / 8};
const u32 bpp{params.GetBytesPerPixel()};
const u32 copy_size{params.width * bpp};
if (params.pitch == copy_size) {
std::memcpy(host_ptr, staging_buffer.data(), memory_size);
std::memcpy(host_ptr, staging_buffer.data(), guest_memory_size);
} else {
u8* start{host_ptr};
const u8* read_to{staging_buffer.data()};
for (u32 h = params.GetHeight(); h > 0; --h) {
for (u32 h = params.height; h > 0; --h) {
std::memcpy(start, read_to, copy_size);
start += params.GetPitch();
start += params.pitch;
read_to += copy_size;
}
}
*/
}
}

14
src/video_core/texture_cache/texture_cache.h
View file

@ -61,6 +61,20 @@ public:
}
}
void FlushRegion(CacheAddr addr, std::size_t size) {
auto surfaces = GetSurfacesInRegion(addr, size);
if (surfaces.empty()) {
return;
}
std::sort(surfaces.begin(), surfaces.end(),
[](const TSurface& a, const TSurface& b) -> bool {
return a->GetModificationTick() < b->GetModificationTick();
});
for (const auto& surface : surfaces) {
FlushSurface(surface);
}
}
TView GetTextureSurface(const Tegra::Texture::FullTextureInfo& config,
const VideoCommon::Shader::Sampler& entry) {
const auto gpu_addr{config.tic.Address()};