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https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
Merge pull request #1533 from FernandoS27/lmem
Implemented Shader Local Memory
This commit is contained in:
commit
d278f25bda
3 changed files with 138 additions and 1 deletions
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@ -208,6 +208,16 @@ enum class UniformType : u64 {
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Double = 5,
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Double = 5,
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};
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};
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enum class StoreType : u64 {
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Unsigned8 = 0,
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Signed8 = 1,
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Unsigned16 = 2,
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Signed16 = 3,
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Bytes32 = 4,
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Bytes64 = 5,
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Bytes128 = 6,
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};
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enum class IMinMaxExchange : u64 {
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enum class IMinMaxExchange : u64 {
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None = 0,
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None = 0,
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XLo = 1,
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XLo = 1,
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@ -747,6 +757,18 @@ union Instruction {
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BitField<44, 2, u64> unknown;
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BitField<44, 2, u64> unknown;
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} ld_c;
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} ld_c;
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union {
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BitField<48, 3, StoreType> type;
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} ldst_sl;
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union {
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BitField<44, 2, u64> unknown;
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} ld_l;
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union {
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BitField<44, 2, u64> unknown;
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} st_l;
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union {
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union {
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BitField<0, 3, u64> pred0;
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BitField<0, 3, u64> pred0;
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BitField<3, 3, u64> pred3;
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BitField<3, 3, u64> pred3;
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@ -1209,6 +1231,7 @@ union Instruction {
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BitField<61, 1, u64> is_b_imm;
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BitField<61, 1, u64> is_b_imm;
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BitField<60, 1, u64> is_b_gpr;
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BitField<60, 1, u64> is_b_gpr;
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BitField<59, 1, u64> is_c_gpr;
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BitField<59, 1, u64> is_c_gpr;
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BitField<20, 24, s64> smem_imm;
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Attribute attribute;
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Attribute attribute;
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Sampler sampler;
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Sampler sampler;
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@ -1232,8 +1255,12 @@ public:
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BRA,
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BRA,
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PBK,
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PBK,
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LD_A,
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LD_A,
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LD_L,
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LD_S,
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LD_C,
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LD_C,
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ST_A,
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ST_A,
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ST_L,
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ST_S,
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LDG, // Load from global memory
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LDG, // Load from global memory
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STG, // Store in global memory
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STG, // Store in global memory
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TEX,
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TEX,
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@ -1490,8 +1517,12 @@ private:
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INST("111000110100---", Id::BRK, Type::Flow, "BRK"),
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INST("111000110100---", Id::BRK, Type::Flow, "BRK"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("1111000011110---", Id::DEPBAR, Type::Synch, "DEPBAR"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111111011---", Id::LD_A, Type::Memory, "LD_A"),
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INST("1110111101001---", Id::LD_S, Type::Memory, "LD_S"),
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INST("1110111101000---", Id::LD_L, Type::Memory, "LD_L"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111110010---", Id::LD_C, Type::Memory, "LD_C"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1110111111110---", Id::ST_A, Type::Memory, "ST_A"),
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INST("1110111101011---", Id::ST_S, Type::Memory, "ST_S"),
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INST("1110111101010---", Id::ST_L, Type::Memory, "ST_L"),
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INST("1110111011010---", Id::LDG, Type::Memory, "LDG"),
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INST("1110111011010---", Id::LDG, Type::Memory, "LDG"),
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INST("1110111011011---", Id::STG, Type::Memory, "STG"),
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INST("1110111011011---", Id::STG, Type::Memory, "STG"),
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INST("110000----111---", Id::TEX, Type::Memory, "TEX"),
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INST("110000----111---", Id::TEX, Type::Memory, "TEX"),
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@ -96,6 +96,11 @@ struct Header {
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}
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}
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} ps;
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} ps;
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};
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};
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u64 GetLocalMemorySize() {
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return (common1.shader_local_memory_low_size |
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(common2.shader_local_memory_high_size << 24));
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}
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};
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};
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static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
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static_assert(sizeof(Header) == 0x50, "Incorrect structure size");
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@ -278,7 +278,7 @@ public:
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const Maxwell3D::Regs::ShaderStage& stage, const std::string& suffix,
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const Maxwell3D::Regs::ShaderStage& stage, const std::string& suffix,
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const Tegra::Shader::Header& header)
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const Tegra::Shader::Header& header)
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: shader{shader}, declarations{declarations}, stage{stage}, suffix{suffix}, header{header},
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: shader{shader}, declarations{declarations}, stage{stage}, suffix{suffix}, header{header},
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fixed_pipeline_output_attributes_used{} {
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fixed_pipeline_output_attributes_used{}, local_memory_size{0} {
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BuildRegisterList();
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BuildRegisterList();
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BuildInputList();
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BuildInputList();
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}
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}
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@ -436,6 +436,25 @@ public:
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shader.AddLine(dest + " = " + src + ';');
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shader.AddLine(dest + " = " + src + ';');
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}
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}
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std::string GetLocalMemoryAsFloat(const std::string& index) {
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return "lmem[" + index + ']';
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}
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std::string GetLocalMemoryAsInteger(const std::string& index, bool is_signed = false) {
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const std::string func{is_signed ? "floatToIntBits" : "floatBitsToUint"};
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return func + "(lmem[" + index + "])";
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}
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void SetLocalMemoryAsFloat(const std::string& index, const std::string& value) {
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shader.AddLine("lmem[" + index + "] = " + value + ';');
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}
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void SetLocalMemoryAsInteger(const std::string& index, const std::string& value,
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bool is_signed = false) {
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const std::string func{is_signed ? "intBitsToFloat" : "uintBitsToFloat"};
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shader.AddLine("lmem[" + index + "] = " + func + '(' + value + ");");
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}
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std::string GetControlCode(const Tegra::Shader::ControlCode cc) const {
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std::string GetControlCode(const Tegra::Shader::ControlCode cc) const {
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switch (cc) {
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switch (cc) {
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case Tegra::Shader::ControlCode::NEU:
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case Tegra::Shader::ControlCode::NEU:
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@ -533,6 +552,7 @@ public:
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void GenerateDeclarations(const std::string& suffix) {
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void GenerateDeclarations(const std::string& suffix) {
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GenerateVertex();
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GenerateVertex();
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GenerateRegisters(suffix);
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GenerateRegisters(suffix);
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GenerateLocalMemory();
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GenerateInternalFlags();
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GenerateInternalFlags();
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GenerateInputAttrs();
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GenerateInputAttrs();
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GenerateOutputAttrs();
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GenerateOutputAttrs();
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@ -578,6 +598,10 @@ public:
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return entry.GetName();
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return entry.GetName();
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}
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}
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void SetLocalMemory(u64 lmem) {
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local_memory_size = lmem;
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}
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private:
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private:
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/// Generates declarations for registers.
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/// Generates declarations for registers.
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void GenerateRegisters(const std::string& suffix) {
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void GenerateRegisters(const std::string& suffix) {
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@ -588,6 +612,15 @@ private:
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declarations.AddNewLine();
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declarations.AddNewLine();
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}
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}
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/// Generates declarations for local memory.
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void GenerateLocalMemory() {
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if (local_memory_size > 0) {
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declarations.AddLine("float lmem[" + std::to_string((local_memory_size - 1 + 4) / 4) +
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"];");
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declarations.AddNewLine();
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}
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}
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/// Generates declarations for internal flags.
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/// Generates declarations for internal flags.
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void GenerateInternalFlags() {
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void GenerateInternalFlags() {
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for (u32 ii = 0; ii < static_cast<u64>(InternalFlag::Amount); ii++) {
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for (u32 ii = 0; ii < static_cast<u64>(InternalFlag::Amount); ii++) {
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@ -895,6 +928,7 @@ private:
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const std::string& suffix;
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const std::string& suffix;
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const Tegra::Shader::Header& header;
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const Tegra::Shader::Header& header;
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std::unordered_set<Attribute::Index> fixed_pipeline_output_attributes_used;
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std::unordered_set<Attribute::Index> fixed_pipeline_output_attributes_used;
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u64 local_memory_size;
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};
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};
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class GLSLGenerator {
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class GLSLGenerator {
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@ -904,6 +938,8 @@ public:
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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: subroutines(subroutines), program_code(program_code), main_offset(main_offset),
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stage(stage), suffix(suffix) {
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stage(stage), suffix(suffix) {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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local_memory_size = header.GetLocalMemorySize();
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regs.SetLocalMemory(local_memory_size);
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Generate(suffix);
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Generate(suffix);
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}
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}
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@ -2324,6 +2360,39 @@ private:
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shader.AddLine("}");
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shader.AddLine("}");
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break;
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break;
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}
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}
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case OpCode::Id::LD_L: {
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// Add an extra scope and declare the index register inside to prevent
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// overwriting it in case it is used as an output of the LD instruction.
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shader.AddLine('{');
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++shader.scope;
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std::string op = '(' + regs.GetRegisterAsInteger(instr.gpr8, 0, false) + " + " +
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std::to_string(instr.smem_imm.Value()) + ')';
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shader.AddLine("uint index = (" + op + " / 4);");
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const std::string op_a = regs.GetLocalMemoryAsFloat("index");
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if (instr.ld_l.unknown != 1) {
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LOG_CRITICAL(HW_GPU, "LD_L Unhandled mode: {}",
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static_cast<unsigned>(instr.ld_l.unknown.Value()));
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UNREACHABLE();
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}
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switch (instr.ldst_sl.type.Value()) {
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case Tegra::Shader::StoreType::Bytes32:
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a, 1, 1);
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break;
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default:
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LOG_CRITICAL(HW_GPU, "LD_L Unhandled type: {}",
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static_cast<unsigned>(instr.ldst_sl.type.Value()));
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UNREACHABLE();
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}
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--shader.scope;
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shader.AddLine('}');
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break;
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}
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case OpCode::Id::ST_A: {
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case OpCode::Id::ST_A: {
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ASSERT_MSG(instr.gpr8.Value() == Register::ZeroIndex,
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ASSERT_MSG(instr.gpr8.Value() == Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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"Indirect attribute loads are not supported");
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@ -2352,6 +2421,37 @@ private:
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break;
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break;
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}
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}
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case OpCode::Id::ST_L: {
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// Add an extra scope and declare the index register inside to prevent
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// overwriting it in case it is used as an output of the LD instruction.
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shader.AddLine('{');
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++shader.scope;
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std::string op = '(' + regs.GetRegisterAsInteger(instr.gpr8, 0, false) + " + " +
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std::to_string(instr.smem_imm.Value()) + ')';
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shader.AddLine("uint index = (" + op + " / 4);");
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if (instr.st_l.unknown != 0) {
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LOG_CRITICAL(HW_GPU, "ST_L Unhandled mode: {}",
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static_cast<unsigned>(instr.st_l.unknown.Value()));
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UNREACHABLE();
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}
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switch (instr.ldst_sl.type.Value()) {
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case Tegra::Shader::StoreType::Bytes32:
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regs.SetLocalMemoryAsFloat("index", regs.GetRegisterAsFloat(instr.gpr0));
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break;
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default:
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LOG_CRITICAL(HW_GPU, "ST_L Unhandled type: {}",
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static_cast<unsigned>(instr.ldst_sl.type.Value()));
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UNREACHABLE();
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}
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--shader.scope;
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shader.AddLine('}');
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break;
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}
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case OpCode::Id::TEX: {
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case OpCode::Id::TEX: {
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Tegra::Shader::TextureType texture_type{instr.tex.texture_type};
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Tegra::Shader::TextureType texture_type{instr.tex.texture_type};
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std::string coord;
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std::string coord;
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@ -3575,6 +3675,7 @@ private:
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const u32 main_offset;
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const u32 main_offset;
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Maxwell3D::Regs::ShaderStage stage;
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Maxwell3D::Regs::ShaderStage stage;
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const std::string& suffix;
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const std::string& suffix;
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u64 local_memory_size;
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ShaderWriter shader;
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ShaderWriter shader;
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ShaderWriter declarations;
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ShaderWriter declarations;
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