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Code Issues Releases Activity

video_core: Fix spelling of "synchronize"

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Morph 2022-10-16 00:50:53 -04:00
parent f706b3bd24
commit ddf5577799
2 changed files with 5 additions and 5 deletions
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2
src/video_core/texture_cache/descriptor_table.h
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@ -18,7 +18,7 @@ class DescriptorTable {
public: public:
explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {} explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {}
[[nodiscard]] bool Synchornize(GPUVAddr gpu_addr, u32 limit) { [[nodiscard]] bool Synchronize(GPUVAddr gpu_addr, u32 limit) {
[[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) { [[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) {
return false; return false;
} }

8
src/video_core/texture_cache/texture_cache.h
View file

@ -193,11 +193,11 @@ void TextureCache<P>::SynchronizeGraphicsDescriptors() {
const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding; const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding;
const u32 tic_limit = maxwell3d->regs.tex_header.limit; const u32 tic_limit = maxwell3d->regs.tex_header.limit;
const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit; const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit;
if (channel_state->graphics_sampler_table.Synchornize(maxwell3d->regs.tex_sampler.Address(), if (channel_state->graphics_sampler_table.Synchronize(maxwell3d->regs.tex_sampler.Address(),
tsc_limit)) { tsc_limit)) {
channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID); channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
} }
if (channel_state->graphics_image_table.Synchornize(maxwell3d->regs.tex_header.Address(), if (channel_state->graphics_image_table.Synchronize(maxwell3d->regs.tex_header.Address(),
tic_limit)) { tic_limit)) {
channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID); channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
} }
@ -209,10 +209,10 @@ void TextureCache<P>::SynchronizeComputeDescriptors() {
const u32 tic_limit = kepler_compute->regs.tic.limit; const u32 tic_limit = kepler_compute->regs.tic.limit;
const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit; const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit;
const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address(); const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address();
if (channel_state->compute_sampler_table.Synchornize(tsc_gpu_addr, tsc_limit)) { if (channel_state->compute_sampler_table.Synchronize(tsc_gpu_addr, tsc_limit)) {
channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID); channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
} }
if (channel_state->compute_image_table.Synchornize(kepler_compute->regs.tic.Address(), if (channel_state->compute_image_table.Synchronize(kepler_compute->regs.tic.Address(),
tic_limit)) { tic_limit)) {
channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID); channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
} }