mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-07-04 23:31:19 +01:00
cb9dd01ffd
This function is called rarely and blocks quite often for a long time. So don't waste power and let the CPU sleep. This might also increase the performance as the other cores might be allowed to clock higher.
342 lines
9.7 KiB
C++
342 lines
9.7 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <array>
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#include <atomic>
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#include <condition_variable>
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#include <list>
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#include <memory>
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#include <mutex>
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#include "common/common_types.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "core/hle/service/nvflinger/buffer_queue.h"
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#include "video_core/dma_pusher.h"
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using CacheAddr = std::uintptr_t;
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inline CacheAddr ToCacheAddr(const void* host_ptr) {
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return reinterpret_cast<CacheAddr>(host_ptr);
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}
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inline u8* FromCacheAddr(CacheAddr cache_addr) {
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return reinterpret_cast<u8*>(cache_addr);
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}
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namespace Core {
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class System;
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}
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namespace VideoCore {
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class RendererBase;
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} // namespace VideoCore
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namespace Tegra {
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enum class RenderTargetFormat : u32 {
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NONE = 0x0,
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RGBA32_FLOAT = 0xC0,
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RGBA32_UINT = 0xC2,
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RGBA16_UNORM = 0xC6,
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RGBA16_UINT = 0xC9,
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RGBA16_FLOAT = 0xCA,
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RG32_FLOAT = 0xCB,
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RG32_UINT = 0xCD,
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RGBX16_FLOAT = 0xCE,
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BGRA8_UNORM = 0xCF,
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BGRA8_SRGB = 0xD0,
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RGB10_A2_UNORM = 0xD1,
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RGBA8_UNORM = 0xD5,
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RGBA8_SRGB = 0xD6,
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RGBA8_SNORM = 0xD7,
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RGBA8_UINT = 0xD9,
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RG16_UNORM = 0xDA,
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RG16_SNORM = 0xDB,
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RG16_SINT = 0xDC,
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RG16_UINT = 0xDD,
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RG16_FLOAT = 0xDE,
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R11G11B10_FLOAT = 0xE0,
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R32_UINT = 0xE4,
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R32_FLOAT = 0xE5,
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B5G6R5_UNORM = 0xE8,
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BGR5A1_UNORM = 0xE9,
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RG8_UNORM = 0xEA,
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RG8_SNORM = 0xEB,
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R16_UNORM = 0xEE,
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R16_SNORM = 0xEF,
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R16_SINT = 0xF0,
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R16_UINT = 0xF1,
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R16_FLOAT = 0xF2,
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R8_UNORM = 0xF3,
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R8_UINT = 0xF6,
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};
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enum class DepthFormat : u32 {
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Z32_FLOAT = 0xA,
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Z16_UNORM = 0x13,
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S8_Z24_UNORM = 0x14,
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Z24_X8_UNORM = 0x15,
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Z24_S8_UNORM = 0x16,
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Z24_C8_UNORM = 0x18,
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Z32_S8_X24_FLOAT = 0x19,
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};
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/// Returns the number of bytes per pixel of each rendertarget format.
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u32 RenderTargetBytesPerPixel(RenderTargetFormat format);
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/// Returns the number of bytes per pixel of each depth format.
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u32 DepthFormatBytesPerPixel(DepthFormat format);
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struct CommandListHeader;
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class DebugContext;
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/**
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* Struct describing framebuffer configuration
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*/
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struct FramebufferConfig {
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enum class PixelFormat : u32 {
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ABGR8 = 1,
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RGB565 = 4,
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BGRA8 = 5,
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};
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VAddr address;
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u32 offset;
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u32 width;
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u32 height;
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u32 stride;
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PixelFormat pixel_format;
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using TransformFlags = Service::NVFlinger::BufferQueue::BufferTransformFlags;
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TransformFlags transform_flags;
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Common::Rectangle<int> crop_rect;
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};
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namespace Engines {
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class Fermi2D;
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class Maxwell3D;
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class MaxwellDMA;
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class KeplerCompute;
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class KeplerMemory;
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} // namespace Engines
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enum class EngineID {
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FERMI_TWOD_A = 0x902D, // 2D Engine
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MAXWELL_B = 0xB197, // 3D Engine
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KEPLER_COMPUTE_B = 0xB1C0,
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KEPLER_INLINE_TO_MEMORY_B = 0xA140,
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MAXWELL_DMA_COPY_A = 0xB0B5,
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};
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class MemoryManager;
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class GPU {
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public:
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explicit GPU(Core::System& system, VideoCore::RendererBase& renderer, bool is_async);
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virtual ~GPU();
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struct MethodCall {
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u32 method{};
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u32 argument{};
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u32 subchannel{};
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u32 method_count{};
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bool IsLastCall() const {
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return method_count <= 1;
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}
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MethodCall(u32 method, u32 argument, u32 subchannel = 0, u32 method_count = 0)
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: method(method), argument(argument), subchannel(subchannel),
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method_count(method_count) {}
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};
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/// Calls a GPU method.
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void CallMethod(const MethodCall& method_call);
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void FlushCommands();
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/// Returns a reference to the Maxwell3D GPU engine.
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Engines::Maxwell3D& Maxwell3D();
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/// Returns a const reference to the Maxwell3D GPU engine.
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const Engines::Maxwell3D& Maxwell3D() const;
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/// Returns a reference to the KeplerCompute GPU engine.
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Engines::KeplerCompute& KeplerCompute();
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/// Returns a reference to the KeplerCompute GPU engine.
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const Engines::KeplerCompute& KeplerCompute() const;
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/// Returns a reference to the GPU memory manager.
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Tegra::MemoryManager& MemoryManager();
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/// Returns a const reference to the GPU memory manager.
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const Tegra::MemoryManager& MemoryManager() const;
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/// Returns a reference to the GPU DMA pusher.
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Tegra::DmaPusher& DmaPusher();
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// Waits for the GPU to finish working
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virtual void WaitIdle() const = 0;
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/// Allows the CPU/NvFlinger to wait on the GPU before presenting a frame.
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void WaitFence(u32 syncpoint_id, u32 value);
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void IncrementSyncPoint(u32 syncpoint_id);
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u32 GetSyncpointValue(u32 syncpoint_id) const;
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void RegisterSyncptInterrupt(u32 syncpoint_id, u32 value);
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bool CancelSyncptInterrupt(u32 syncpoint_id, u32 value);
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std::unique_lock<std::mutex> LockSync() {
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return std::unique_lock{sync_mutex};
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}
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bool IsAsync() const {
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return is_async;
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}
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/// Returns a const reference to the GPU DMA pusher.
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const Tegra::DmaPusher& DmaPusher() const;
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struct Regs {
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static constexpr size_t NUM_REGS = 0x100;
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union {
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struct {
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INSERT_UNION_PADDING_WORDS(0x4);
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struct {
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u32 address_high;
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u32 address_low;
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GPUVAddr SemaphoreAddress() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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} semaphore_address;
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u32 semaphore_sequence;
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u32 semaphore_trigger;
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INSERT_UNION_PADDING_WORDS(0xC);
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// The puser and the puller share the reference counter, the pusher only has read
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// access
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u32 reference_count;
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INSERT_UNION_PADDING_WORDS(0x5);
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u32 semaphore_acquire;
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u32 semaphore_release;
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u32 fence_value;
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union {
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BitField<4, 4, u32> operation;
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BitField<8, 8, u32> id;
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} fence_action;
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INSERT_UNION_PADDING_WORDS(0xE2);
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// Puller state
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u32 acquire_mode;
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u32 acquire_source;
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u32 acquire_active;
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u32 acquire_timeout;
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u32 acquire_value;
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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virtual void Start() = 0;
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/// Push GPU command entries to be processed
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virtual void PushGPUEntries(Tegra::CommandList&& entries) = 0;
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/// Swap buffers (render frame)
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virtual void SwapBuffers(const Tegra::FramebufferConfig* framebuffer) = 0;
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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virtual void FlushRegion(CacheAddr addr, u64 size) = 0;
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/// Notify rasterizer that any caches of the specified region should be invalidated
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virtual void InvalidateRegion(CacheAddr addr, u64 size) = 0;
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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virtual void FlushAndInvalidateRegion(CacheAddr addr, u64 size) = 0;
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protected:
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virtual void TriggerCpuInterrupt(u32 syncpoint_id, u32 value) const = 0;
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private:
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void ProcessBindMethod(const MethodCall& method_call);
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void ProcessSemaphoreTriggerMethod();
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void ProcessSemaphoreRelease();
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void ProcessSemaphoreAcquire();
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/// Calls a GPU puller method.
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void CallPullerMethod(const MethodCall& method_call);
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/// Calls a GPU engine method.
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void CallEngineMethod(const MethodCall& method_call);
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/// Determines where the method should be executed.
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bool ExecuteMethodOnEngine(const MethodCall& method_call);
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protected:
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std::unique_ptr<Tegra::DmaPusher> dma_pusher;
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Core::System& system;
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VideoCore::RendererBase& renderer;
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private:
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std::unique_ptr<Tegra::MemoryManager> memory_manager;
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/// Mapping of command subchannels to their bound engine ids
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std::array<EngineID, 8> bound_engines = {};
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/// 3D engine
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std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
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/// 2D engine
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std::unique_ptr<Engines::Fermi2D> fermi_2d;
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/// Compute engine
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std::unique_ptr<Engines::KeplerCompute> kepler_compute;
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/// DMA engine
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std::unique_ptr<Engines::MaxwellDMA> maxwell_dma;
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/// Inline memory engine
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std::unique_ptr<Engines::KeplerMemory> kepler_memory;
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std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
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std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
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std::mutex sync_mutex;
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std::condition_variable sync_cv;
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const bool is_async;
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(GPU::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(semaphore_address, 0x4);
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ASSERT_REG_POSITION(semaphore_sequence, 0x6);
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ASSERT_REG_POSITION(semaphore_trigger, 0x7);
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ASSERT_REG_POSITION(reference_count, 0x14);
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ASSERT_REG_POSITION(semaphore_acquire, 0x1A);
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ASSERT_REG_POSITION(semaphore_release, 0x1B);
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ASSERT_REG_POSITION(fence_value, 0x1C);
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ASSERT_REG_POSITION(fence_action, 0x1D);
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ASSERT_REG_POSITION(acquire_mode, 0x100);
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ASSERT_REG_POSITION(acquire_source, 0x101);
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ASSERT_REG_POSITION(acquire_active, 0x102);
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ASSERT_REG_POSITION(acquire_timeout, 0x103);
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ASSERT_REG_POSITION(acquire_value, 0x104);
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#undef ASSERT_REG_POSITION
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} // namespace Tegra
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