mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-14 17:06:48 +00:00
98e05ee4b7
* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
49 lines
No EOL
1.4 KiB
C#
49 lines
No EOL
1.4 KiB
C#
using ARMeilleure.IntermediateRepresentation;
|
|
using System;
|
|
|
|
namespace ARMeilleure.Decoders
|
|
{
|
|
class OpCode : IOpCode
|
|
{
|
|
public ulong Address { get; }
|
|
public int RawOpCode { get; }
|
|
|
|
public int OpCodeSizeInBytes { get; protected set; } = 4;
|
|
|
|
public InstDescriptor Instruction { get; protected set; }
|
|
|
|
public RegisterSize RegisterSize { get; protected set; }
|
|
|
|
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
|
|
|
|
public OpCode(InstDescriptor inst, ulong address, int opCode)
|
|
{
|
|
Instruction = inst;
|
|
Address = address;
|
|
RawOpCode = opCode;
|
|
|
|
RegisterSize = RegisterSize.Int64;
|
|
}
|
|
|
|
public int GetPairsCount() => GetBitsCount() / 16;
|
|
public int GetBytesCount() => GetBitsCount() / 8;
|
|
|
|
public int GetBitsCount()
|
|
{
|
|
switch (RegisterSize)
|
|
{
|
|
case RegisterSize.Int32: return 32;
|
|
case RegisterSize.Int64: return 64;
|
|
case RegisterSize.Simd64: return 64;
|
|
case RegisterSize.Simd128: return 128;
|
|
}
|
|
|
|
throw new InvalidOperationException();
|
|
}
|
|
|
|
public OperandType GetOperandType()
|
|
{
|
|
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
|
|
}
|
|
}
|
|
} |