FICTURE7 a9343c9364 Refactor PtcInfo (#2625) ... * Refactor `PtcInfo` This change reduces the coupling of `PtcInfo` by moving relocation tracking to the backend. `RelocEntry`s remains as `RelocEntry`s through out the pipeline until it actually needs to be written to the PTC streams. Keeping this representation makes inspecting and manipulating relocations after compilations less painful. This is something I needed to do to patch relocations to 0 to diff dumps. Contributes to #1125. * Turn `Symbol` & `RelocInfo` into readonly structs * Add documentation to `CompiledFunction` * Remove `Compiler.Compile<T>` Remove `Compiler.Compile<T>` and replace it by `Map<T>` of the `CompiledFunction` returned.		2021-09-14 01:23:37 +02:00
..
Assembler.cs	Refactor PtcInfo (#2625)	2021-09-14 01:23:37 +02:00
CallConvName.cs
CallingConvention.cs
CodeGenCommon.cs
CodeGenContext.cs	Refactor PtcInfo (#2625)	2021-09-14 01:23:37 +02:00
CodeGenerator.cs	Refactor PtcInfo (#2625)	2021-09-14 01:23:37 +02:00
HardwareCapabilities.cs	CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650)	2020-11-18 19:35:54 +01:00
IntrinsicInfo.cs
IntrinsicTable.cs	CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests. (#1894)	2021-01-20 09:12:33 +11:00
IntrinsicType.cs	Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). (#1630)	2020-12-07 10:37:07 +01:00
PreAllocator.cs	Reduce JIT GC allocations (#2515)	2021-08-17 15:08:34 -03:00
X86Condition.cs
X86Instruction.cs	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
X86Optimizer.cs	Reduce JIT GC allocations (#2515)	2021-08-17 15:08:34 -03:00
X86Register.cs