mirror of
https://github.com/CTCaer/hekate.git
synced 2024-12-22 16:12:03 +00:00
ldr/bl: manage arbiter
This commit is contained in:
parent
985c513770
commit
1214ab0e02
2 changed files with 10 additions and 1 deletions
|
@ -1173,6 +1173,9 @@ int hos_launch(ini_sec_t *cfg)
|
|||
CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD);
|
||||
CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_AHBDMA) | BIT(CLK_H_APBDMA) | BIT(CLK_H_USB2);
|
||||
|
||||
// Reset arbiter.
|
||||
hw_config_arbiter(true);
|
||||
|
||||
// Scale down RAM OC if enabled.
|
||||
minerva_prep_boot_freq();
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019 CTCaer
|
||||
* Copyright (c) 2019-2024 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
@ -67,6 +67,12 @@ void loader_main()
|
|||
CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
|
||||
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
|
||||
|
||||
// Set arbiter.
|
||||
ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x12412D1;
|
||||
ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x0000000;
|
||||
ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x220244A;
|
||||
ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320369B;
|
||||
|
||||
// Get Payload size.
|
||||
u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size.
|
||||
payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add compiler alignment.
|
||||
|
|
Loading…
Reference in a new issue