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bdk: hwinit: add arbiter config
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parent
16eb6a3c44
commit
985c513770
2 changed files with 27 additions and 2 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -93,6 +93,24 @@ static void _config_oscillators()
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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void hw_config_arbiter(bool reset)
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{
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if (reset)
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{
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ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x0040090;
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ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x12024C2;
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ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x2201209;
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ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320365B;
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}
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else
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{
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ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x12412D1;
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ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x0000000;
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ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x220244A;
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ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320369B;
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}
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}
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// The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula.
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static void _config_gpios(bool nx_hoag)
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{
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@ -406,6 +424,9 @@ void hw_init()
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PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ;
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}
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// Set arbiter.
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hw_config_arbiter(false);
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// Initialize External memory controller and configure DRAM parameters.
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sdram_init();
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@ -439,6 +460,9 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic)
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// Flush/disable MMU cache.
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bpmp_mmu_disable();
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// Reset arbiter.
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hw_config_arbiter(true);
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// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
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if (tegra_t210)
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{
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2021 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -28,6 +28,7 @@ extern u32 hw_rst_reason;
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void hw_init();
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void hw_reinit_workaround(bool coreboot, u32 magic);
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void hw_config_arbiter(bool reset);
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u32 hw_get_chip_id();
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#endif
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