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bdk: smmu: powergate ccplex after enabling smmu
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parent
fb31cb2926
commit
3a4fa12f42
4 changed files with 19 additions and 39 deletions
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@ -23,27 +23,18 @@
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#include <soc/t210.h>
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#include <mem/mc_t210.h>
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#include <mem/smmu.h>
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#include <utils/aarch64_util.h>
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bool smmu_used = false;
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u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR;
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//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
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// Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1;
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u8 smmu_payload[] __attribute__((aligned(16))) = {
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0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
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0xC1, 0x00, 0x00, 0x58, // 0x00: LDR X1, =0x70019010
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0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1
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0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1]
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0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS
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0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH
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0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop
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0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0
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0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1]
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0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000
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0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0
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0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG
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0x00, 0x00, 0x00, 0x00, // 0x2C:
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0x00, 0x00, 0x00, 0x00, // 0x30: secmon address
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0x00, 0x00, 0x00, 0x00 // 0x34:
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0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG
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};
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void *page_alloc(u32 num)
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@ -76,7 +67,7 @@ void smmu_flush_all()
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smmu_flush_regs();
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}
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void smmu_init(u32 secmon_base)
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void smmu_init()
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{
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MC(MC_SMMU_PTB_ASID) = 0;
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MC(MC_SMMU_PTB_DATA) = 0;
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@ -84,31 +75,22 @@ void smmu_init(u32 secmon_base)
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MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F;
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MC(MC_SMMU_PTC_FLUSH) = 0;
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MC(MC_SMMU_TLB_FLUSH) = 0;
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// Set the secmon address
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*(u32 *)(smmu_payload + 0x30) = secmon_base;
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}
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void smmu_enable()
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{
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if (smmu_used)
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static bool enabled = false;
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if (enabled)
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return;
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ccplex_boot_cpu0((u32)smmu_payload, true);
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smmu_used = true;
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msleep(150);
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ccplex_boot_cpu0((u32)smmu_payload, false);
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msleep(100);
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ccplex_powergate_cpu0();
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smmu_flush_all();
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}
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bool smmu_is_used()
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{
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return smmu_used;
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}
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void smmu_exit()
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{
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*(u32 *)(smmu_payload + 0x14) = _NOP();
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enabled = true;
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}
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u32 *smmu_init_domain4(u32 dev_base, u32 asid)
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -72,10 +73,8 @@ void *page_alloc(u32 num);
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u32 *smmu_alloc_pdir();
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void smmu_flush_regs();
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void smmu_flush_all();
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void smmu_init(u32 secmon_base);
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void smmu_init();
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void smmu_enable();
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bool smmu_is_used();
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void smmu_exit();
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u32 *smmu_init_domain4(u32 dev_base, u32 asid);
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u32 *smmu_get_pte(u32 *pdir, u32 iova);
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void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr);
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2023 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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* Copyright (c) 2018 balika011
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*
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* This program is free software; you can redistribute it and/or modify it
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@ -146,10 +146,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt)
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{
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// Init SMMU translation for TSEC.
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pdir = smmu_init_for_tsec();
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smmu_init(tsec_ctxt->secmon_base);
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// Enable SMMU
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if (!smmu_is_used())
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smmu_enable();
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smmu_init();
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// Enable SMMU.
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smmu_enable();
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// Clock reset controller.
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car = page_alloc(1);
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2021 CTCaer
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* Copyright (c) 2018-2024 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -35,7 +35,6 @@ typedef struct _tsec_ctxt_t
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u32 type;
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void *pkg1;
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u32 pkg11_off;
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u32 secmon_base;
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} tsec_ctxt_t;
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int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt);
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