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501 commits 2 branches 75 tags 6.7 MiB
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37 commits

Author SHA1 Message Date
CTCaer
51985ed2ca sdmmc v2: Bus/IO clock refactoring and fixes 
Use the exact same clocks with HOS and utilize low jitter clock parents.

Add back our compatibility mode and the missing timeout clock parent.

Hekate main will continue to use PLLP clock parent for all.
 2020-04-30 01:26:55 +03:00
CTCaer
034f680a8e sd fs: Move sd init/mount/helpers to their own object 2020-04-29 23:20:18 +03:00
CTCaer
5b0a0070c7 sdmmc v2: Refactor everything 2020-04-29 18:53:29 +03:00
CTCaer
9a5cfdff4c gpio: Upgrade GPIO driver 
Use macros to get bank addresses and add full configuration support.
 2020-04-27 09:51:25 +03:00
CTCaer
cb3b1bf6e1 irq: Add Legacy Interrupt Controller driver 2020-04-27 09:49:00 +03:00
CTCaer
b4d2df8111 Name various t210 registers 2020-04-27 09:47:47 +03:00
CTCaer
f5040f1e41 Update and add missing copyrights 
Probably more need to change.
 2020-03-14 09:24:24 +02:00
CTCaer
144d6fd3f6 i2c: Update drivers 
Adds support for 8 byte transfers needed by touch driver changes.
 2020-03-13 10:25:27 +02:00
CTCaer
03a8a11933 Small fixes and changes 
- Allow printing of more log on HOS boot when LOGS are OFF.
- A small name refactoring
- Add battery warning symbol when battery < 3200mV
 2020-03-03 04:11:13 +02:00
CTCaer
4c1f67d022 Fix build errors 2020-01-19 15:22:59 +02:00
CTCaer
4d53f21387 mtc: Clear init magic on chainload 
Fixes a hang caused when rebooting 2 payload from L4T with old hekate in vendor partition.

L4T does not overwrite the nyx storage where the Minerva configuration is stored.
This makes new Minerva parse the wrong tables from old hekate and eventually hang the RAM, which causes an exception on BPMP.
 2020-01-14 23:41:15 +02:00
CTCaer
c99a87dd09 clock: Move PLLC config from bpmp.c to clock.c 2020-01-07 06:46:22 +02:00
CTCaer
009db77426 bpmp: Switch to PLLC for SCLK/BPMP clock source 2020-01-07 06:26:29 +02:00
CTCaer
2f43145131 uart: Add invert, get/set IIR and fifo empty functions 2019-12-16 22:16:40 +02:00
CTCaer
e3fca2bce5 uart: Add timeout and len report to uart receive 2019-12-16 22:15:21 +02:00
CTCaer
da112a0ae9 uart: Proper uart init 2019-12-16 22:12:09 +02:00
CTCaer
7604239237 bpmp: Update driver to latest 2019-12-14 22:21:42 +02:00
CTCaer
f256bd5909 Move all I/DRAM addresses into a memory map 
Many addresses were moved around to pack the memory usage!
 2019-12-08 02:23:03 +02:00
CTCaer
0290892b23 nyx hw reconfig: Add fan and 5V regulators deinit 
Additionally re-arrange minerva and mmu after these.
 2019-12-08 01:41:57 +02:00
Kostas Missos
48c15a8fde nyx: Release the shackles 2019-12-07 20:16:38 +02:00
Kostas Missos
0b45a5a11a bpmp: Reduce freq to 589MHz 
3 users had issues with 602MHz.
This will probably bring the SoC binning compatibility to 100%.

Additionally, make it easy to change default boost frequency.

The tiny loss in perf, will be mitigated in Nyx. (It's actually even faster)
 2019-12-07 02:01:29 +02:00
Kostas Missos
bc7dec2e61 bpmp: Add forcable maintenance 
+ Fix build issues
 2019-12-07 01:47:44 +02:00
CTCaer
dd8ec0d28b clock: Always wait 2us before deasserting reset 2019-12-04 21:32:51 +02:00
CTCaer
0b1eebefe1 Small refactor and bugfixes 2019-12-04 21:31:39 +02:00
CTCaer
65fbdfddbf kfuse: Ensure that kfuse is ready 100% for tsec 2019-10-22 18:57:51 +03:00
Kostas Missos
7c42f72b8a refactor: Remove all unwanted whitespace 2019-10-18 18:02:06 +03:00
CTCaer
23e246f224 i2c: Add missing clocks + more refactoring 2019-09-12 23:11:17 +03:00
CTCaer
3028568019 pmc-ccplex: Have proper Power Domain toggling 2019-09-12 23:09:38 +03:00
CTCaer
a8d529cf6a Refactoring and comment adding 2019-09-12 23:08:38 +03:00
CTCaer
c5b64a2b58 tsec: Don't disable HOST1x clock because it's used 
Tsec keys function always disabled host1x clock after running.
This interferes with display interface and disables further window frame syncing.
Display_end code already handles disable and reset of said clock.

It also fixes an ancient bug that was mitigated by removing the 5 frame sync on HOST1X_SYNC_SYNCPT_9 at channel 0:
5fd9daa364 (diff-6b0c56eab8515465d559ff0ea73a22c3L152)
 2019-09-11 02:19:41 +03:00
Kostas Missos
718e502983 Add more register names + refactoring 2019-09-09 16:56:37 +03:00
CTCaer
f622d57f6b utils: Fix ms timer accuracy 
Additionally add BPMP delay timers for future use.
 2019-08-28 01:33:38 +03:00
CTCaer
3472e7e7fb Various bugfixes 2019-08-28 01:08:57 +03:00
ctcaer@gmail.com
5b919cb12e [Touch] Fix touch hang for some SoC revisions 
Fixes the hang on Nyx boot.
 2019-07-06 22:24:03 +03:00
ctcaer@gmail.com
138da26a9a [BPMP] Fix cache coherency issues 
+ Fix framebuffer memfetcher for some SoC revisions.
 2019-07-06 22:22:47 +03:00
ctcaer@gmail.com
08b84384a6 Bugfixes and cleanup 2019-07-06 22:08:37 +03:00
ctcaer@gmail.com
c41f98039c [Nyx] Introducing hekate GUI, named Nyx! 
Version 0.8.0.

Expect dragons!
 2019-06-30 04:03:00 +03:00