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1535 commits 2 branches 75 tags 5.5 MiB
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Author SHA1 Message Date
CTCaer
01a8f30925 nyx: add contact me for unknown ram chips 2023-08-22 16:44:03 +03:00
CTCaer
d73a3fdd7c bdk: sdram: name 1a micron ram chips 
Again, as with 3rd gen samsung and hynix, that's an educated guess.
 2023-08-22 14:44:27 +03:00
CTCaer
fdf0dcc636 bdk: joycon: add info about sio imu report 2023-08-22 14:36:23 +03:00
CTCaer
976a02f8bc nyx: clock: fix year off-by-one 2023-08-07 21:12:18 +03:00
CTCaer
187b6d843e nyx: emummc: allow migrating emummc backup 
Now if an eMMC backup is not found, emuMMC backup will be used.
 2023-08-07 21:11:17 +03:00
CTCaer
6de29094fe nyx: gfx: add column control 
gfx_getpos/setpos can now get/set column offset.
setpos column can be fully custom. Otherwise GFX_COL_KEEP or GFX_COL_AUTO (2 columns) can be used.

Additionally, always restore column when printing debug info in log screen.
 2023-08-07 21:09:37 +03:00
CTCaer
f2bdc3f47c bdk: i2c: fix stack buffer overflow 2023-08-07 21:02:20 +03:00
CTCaer
09b1efe2a4 nyx: info: use updated defines 2023-07-31 17:09:04 +03:00
CTCaer
bb0a1fd0a2 minerva: add freqs up to 2366 MHz 2023-07-31 17:05:09 +03:00
CTCaer
1cc97ebc51 bdk: update various comments 2023-07-31 17:03:15 +03:00
CTCaer
1e28320e5a bdk: t210: add more mmio addresses 
And simplify relevant drivers that hardcoded them.
 2023-07-31 16:59:15 +03:00
CTCaer
0fe17cfb41 l4t: add latest api version info 2023-07-28 15:42:16 +03:00
CTCaer
91393700ff nyx: use restore/emummc folder for restoring 
In order to avoid mistakes, emuMMC can now only be restored from `backup/{emmc_sn}/restore/emummc`.
 2023-07-28 04:07:43 +03:00
CTCaer
cb964fe5d2 l4t: allow ram undervolting 2023-07-28 04:04:03 +03:00
CTCaer
010b08d4c7 l4t: t210b01: set real dram rate by default 
Since Arachne Register Cell (ARC) is now final and stable,
automatically set rated DRAM frequency for T210B01 by default.
1866 MHz for old ones and 2133 MHz for newer ones.

Setting anything from 1600000 and lower will disable that.
 2023-07-28 04:03:01 +03:00
CTCaer
b5fcdad33f nyx: info: improve ram channel/rank detection 2023-07-28 03:40:32 +03:00
CTCaer
6061bb5213 nyx: info: add public key info 
And remove LOT Code 1 since it's not used.
 2023-07-28 03:38:40 +03:00
CTCaer
221614212a nyx: info: add more cal0 info 
Touch vendor, IMU type/mount and analog stick types.
 2023-07-28 03:36:10 +03:00
CTCaer
5b94e8cf8a nyx: info: use fuel gauge reg dump function 2023-07-28 03:35:08 +03:00
CTCaer
f291a5cfa7 bdk: max17050: add reg dumping 2023-07-28 03:34:11 +03:00
CTCaer
7e397b3403 nyx: options: change autorcm icon 2023-07-28 03:33:09 +03:00
CTCaer
f35c5b0596 nyx: fix first time config save unmounting 
SD card should not get unmounted on the first boot without hekate_ipl.ini.
Move sd card mounting management outside of it.
 2023-07-28 03:32:33 +03:00
CTCaer
b142ca0f33 nyx: info: use new fuse names 2023-07-28 03:29:24 +03:00
CTCaer
21da947c02 nyx: hos: deduplicate cal0 dumping 2023-07-28 03:28:21 +03:00
CTCaer
317abb2f4e hekate: add bootwait for each entry 
Allow overriding global bootwait with the one from boot entry.
 2023-07-28 03:23:03 +03:00
CTCaer
d3567736c8 hos: allow overriding uCID 2023-07-28 03:06:20 +03:00
CTCaer
9187fa7a8c bdk: fuse: add all t210b01 fuses 
And use B01 to distinguish the ones only on that SoC.
 2023-07-22 07:10:12 +03:00
CTCaer
b9bc35a22e bdk: dram: correct old comments 2023-07-21 18:39:46 +03:00
CTCaer
6e954f5cdf nyx: provide the raw calib for Lite gamepad 
Let L4T driver manage it.
 2023-06-11 13:29:04 +03:00
CTCaer
d7ad9b874b bdk: use the typedefs on jc calib 2023-06-11 13:27:48 +03:00
CTCaer
820e6d5a6e bdk: update cal0 struct 2023-06-10 23:48:45 +03:00
CTCaer
0215d16405 Bump hekate to v6.0.4 and Nyx to v1.5.4 2023-06-09 11:08:13 +03:00
CTCaer
c0c0e34ef0 nyx: info: update dram info 2023-06-09 11:04:31 +03:00
CTCaer
581ac8ec33 nyx: info: always report errors for eMMC 
Even if init fails.
 2023-06-09 11:04:07 +03:00
CTCaer
26bf148188 nyx: add Lite gamepad calibration data dumping 
Adds calibration data dumping via the Joycon BT pairing dumping function.

Calibration for everything about Sio is dumped. So Sticks and IMU.
 2023-06-09 11:03:29 +03:00
CTCaer
dc8f6beb8d nyx: info: make cal0 dumping public 2023-06-09 11:01:08 +03:00
CTCaer
25b181bf36 nyx: add missing newlines 
Change line since the text does not fit like that in these places, effectively breaking text color.
 2023-06-09 10:59:03 +03:00
CTCaer
66e5e128f6 l4t: adjust revision amidst the new changes 
Also add helpful message if files are missing.
 2023-06-09 10:56:39 +03:00
CTCaer
84822726cb l4t: add fine tuned voltage support for DRAM 
1000-1175mV for T210 VDDIO/Q via `ram_oc_vdd2`
1000-1175mV for T210B01 VDDIO and 600-650mV for VDDQ via `ram_oc_vdd2` and `ram_oc_vddq`.
 2023-06-09 10:55:32 +03:00
CTCaer
b6e1e0d412 l4t: add bpmp-fw support for T210 2023-06-09 10:53:03 +03:00
CTCaer
496737248c l4t: there was never a need to normalize dram freq 2023-06-09 10:51:31 +03:00
CTCaer
4f52e1f24a l4t: refactor bpmp-fw defines for T210B01 2023-06-09 10:50:29 +03:00
CTCaer
3f9c7a7da6 hos: prep boot freq in minerva for cfw also 2023-06-09 10:41:53 +03:00
CTCaer
93ed4d0899 bdk: emc: add temp and feature reporting defines 2023-06-09 10:38:24 +03:00
CTCaer
01afd2de56 bdk: sdmmc: properly report comp pad status 
The reporting of the resistor being shorted or open was swapped. Fix that so it's immediately known what's the issue.
 2023-06-09 10:37:47 +03:00
CTCaer
d621d96af1 bdk: sdmmc: refactor comments 2023-06-09 10:36:29 +03:00
CTCaer
b674624ad0 bdk: timer: add instruction sleep 
usage:
`isleep(ILOOP(instructions))`

Each loop is 3 cycles, or approximately 7.35ns on 408MHz CPU clock.
 2023-06-09 10:33:11 +03:00
CTCaer
191a0533d9 bdk: clock: add more known pto ids 2023-06-09 10:29:47 +03:00
CTCaer
8502731fbd bdk: tsec: refactor some register names 2023-06-09 10:28:28 +03:00
CTCaer
18f3a1b70c bdk: max77620: reduce max DRAM VDDIO/Q 
Reduce allowed VDDIO/VDDQfor T210B01 and VDDIO for T210B01.
 2023-06-09 10:24:55 +03:00