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hekate/bdk/soc
CTCaer d258c82d52 bdk: sdmmc: add UHS DDR200 support
The bdk flag BDK_SDMMC_UHS_DDR200_SUPPORT can be used to enable it.

SD Card DDR200 (DDR208) support

Proper procedure:
1. Check that Vendor Specific Command System is supported.
   Used as Enable DDR200 Bus.
2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6.
   Access Mode group is left to default 0 (SDR12).
3. Setup clock to 200 or 208 MHz.
4. Set host to DDR bus mode that supports such high clocks.
   Some hosts have special mode, others use DDR50 and others HS400.
5. Execute Tuning.

The true validation that this value in Group 2 activates it, is that DDR50 bus
and clocks/timings work fully after that point.

On Tegra X1, that can be done with DDR50 host mode.
Tuning though can't be done automatically on any DDR mode.
So it needs to be done manually and selected tap will be applied from the
biggest sampling window.

Finally, all that simply works, because the marketing materials for DDR200 are
basically overstatements to sell the feature. DDR200 is simply SDR104 in DDR mode,
so sampling on rising and falling edge and with variable output data window.
It can be supported by any host that is fast enough to support DDR at 200/208MHz
and can do hw/sw tuning for finding the proper sampling window in that mode.

Using a SDMMC controller on DDR200 mode at 400MHz, has latency allowance implications. The MC/EMC must be clocked enough to be able to serve the requests in time (512B in 1.28 ns).
2023-03-31 08:54:13 +03:00
..
actmon.c bdk: add activity monitor driver 2022-01-20 12:32:02 +02:00
actmon.h bdk: add activity monitor driver 2022-01-20 12:32:02 +02:00
bpmp.c bdk: stylistic corrections 2023-02-11 23:46:38 +02:00
bpmp.h bdk: stylistic corrections 2023-02-11 23:46:38 +02:00
ccplex.c bdk: sdmmc: timing changes 2022-10-11 04:05:12 +03:00
ccplex.h Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
clock.c bdk: sdmmc: add UHS DDR200 support 2023-03-31 08:54:13 +03:00
clock.h bdk: clock: rename clock_t to clk_rst_t 2023-03-31 08:18:45 +03:00
fuse.c bdk: sdram: add new dram ids/configs 2022-10-11 10:38:43 +03:00
fuse.h bdk: small refactor 2022-10-11 06:16:38 +03:00
gpio.c bdk: gpio: add debounce set function 2023-03-31 07:43:16 +03:00
gpio.h bdk: gpio: add debounce set function 2023-03-31 07:43:16 +03:00
hw_init.c bdk: hwdeinit: restore order of bpmp clock set 2023-02-22 14:48:43 +02:00
hw_init.h bdk: hw init: remove support for broken hwinits 2023-02-11 23:19:56 +02:00
i2c.c bdk: i2c: fix send packet mode 2022-10-11 14:40:58 +03:00
i2c.h i2c: Fix packet mode 2020-10-20 10:37:33 +03:00
irq.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
irq.h Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
kfuse.c Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
kfuse.h Utilize BIT macro everywhere 2020-11-26 01:41:45 +02:00
pinmux.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
pinmux.h bdk: small refactor 2022-10-11 06:16:38 +03:00
pmc.c bdk: pmc: extend pmc scratch locker 2022-10-11 14:41:42 +03:00
pmc.h bdk: slight refactor 2022-12-19 05:22:55 +02:00
pmc_lp0_t210.h Utilize hekate's BDK for hekate main and Nyx 2020-06-14 16:45:45 +03:00
t210.h bdk: small refactor 2022-10-11 06:16:38 +03:00
timer.c bdk: watchdog: clear timer interrupt also in handling 2022-07-11 22:10:41 +03:00
timer.h bdk: timer: add timer/watchdog driver 2022-06-27 10:20:25 +03:00
uart.c bdk: whitespace refactor 2022-07-11 22:10:11 +03:00
uart.h uart: rename print to printf 2022-06-25 05:42:42 +03:00