2018-12-17 21:22:08 +00:00
|
|
|
/*
|
2019-04-08 03:00:49 +01:00
|
|
|
* Copyright (c) 2018-2019 Atmosphère-NX
|
2018-12-17 21:22:08 +00:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
* version 2, as published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
* more details.
|
|
|
|
*
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <stdint.h>
|
|
|
|
|
|
|
|
#include "utils.h"
|
|
|
|
#include "misc.h"
|
|
|
|
#include "fuse.h"
|
|
|
|
#include "sysreg.h"
|
|
|
|
#include "pmc.h"
|
|
|
|
|
2018-12-17 22:40:30 +00:00
|
|
|
void misc_configure_device_dbg_settings(void) {
|
2018-12-17 21:22:08 +00:00
|
|
|
/* Enable RTCK daisychaining by setting TBE bit. */
|
|
|
|
APB_MISC_PP_CONFIG_CTL_0 = 0x80;
|
|
|
|
|
|
|
|
/* Literally none of this is documented in the TRM, lol. */
|
|
|
|
if (FUSE_CHIP_REGS->FUSE_SECURITY_MODE == 1) {
|
|
|
|
uint32_t secure_boot_val = 0b0100; /* Sets NIDEN for aarch64. */
|
|
|
|
uint32_t misc_val = 0x40;
|
|
|
|
if (APBDEV_PMC_STICKY_BITS_0 & 0x40) {
|
|
|
|
misc_val = 0x0;
|
|
|
|
} else {
|
|
|
|
secure_boot_val = 0b1101; /* Sets SPNIDEN, NIDEN, DBGEN for aarch64. */
|
|
|
|
}
|
|
|
|
SB_PFCFG_0 = (SB_PFCFG_0 & ~0b1111) | secure_boot_val; /* Configures debug bits. */
|
|
|
|
APB_MISC_PP_CONFIG_CTL_0 |= misc_val; /* Undocumented, seems to control invasive debugging/JTAG. */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set sticky bits based SECURITY_MODE. */
|
|
|
|
APBDEV_PMC_STICKY_BITS_0 |= FUSE_CHIP_REGS->FUSE_SECURITY_MODE;
|
|
|
|
|
|
|
|
/* Set E_INPUT in PINMUX_AUX_GPIO_PA6_0 */
|
|
|
|
PINMUX_AUX_GPIO_PA6_0 |= 0x40;
|
|
|
|
}
|
2018-12-17 22:40:30 +00:00
|
|
|
|
|
|
|
void misc_restore_ram_svop(void) {
|
|
|
|
/* This sets CFG2TMC_RAM_SVOP_PDP to 0x2. */
|
2019-01-20 10:37:04 +00:00
|
|
|
APB_MISC_GP_ASDBGREG_0 = (APB_MISC_GP_ASDBGREG_0 & 0xFCFFFFFF) | 0x02000000;
|
2018-12-17 22:40:30 +00:00
|
|
|
}
|