2020-10-31 23:34:06 +00:00
|
|
|
/*
|
2021-10-04 20:59:10 +01:00
|
|
|
* Copyright (c) Atmosphère-NX
|
2020-10-31 23:34:06 +00:00
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
|
* version 2, as published by the Free Software Foundation.
|
|
|
|
|
*
|
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
|
* more details.
|
|
|
|
|
*
|
|
|
|
|
* You should have received a copy of the GNU General Public License
|
|
|
|
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
*/
|
|
|
|
|
#pragma once
|
|
|
|
|
#include <vapours/common.hpp>
|
|
|
|
|
#include <vapours/assert.hpp>
|
|
|
|
|
#include <vapours/literals.hpp>
|
|
|
|
|
#include <vapours/util.hpp>
|
|
|
|
|
#include <vapours/results.hpp>
|
|
|
|
|
#include <vapours/reg.hpp>
|
|
|
|
|
|
|
|
|
|
#define I2C_I2C_CNFG (0x000)
|
|
|
|
|
#define I2C_I2C_CMD_ADDR0 (0x004)
|
|
|
|
|
#define I2C_I2C_CMD_DATA1 (0x00C)
|
|
|
|
|
#define I2C_I2C_STATUS (0x01C)
|
2020-11-01 00:58:38 +00:00
|
|
|
#define I2C_PACKET_TRANSFER_STATUS (0x058)
|
|
|
|
|
#define I2C_FIFO_CONTROL (0x05C)
|
2020-11-01 02:14:43 +00:00
|
|
|
#define I2C_FIFO_STATUS (0x060)
|
|
|
|
|
#define I2C_INTERRUPT_MASK_REGISTER (0x064)
|
2020-10-31 23:34:06 +00:00
|
|
|
#define I2C_INTERRUPT_STATUS_REGISTER (0x068)
|
|
|
|
|
#define I2C_CLK_DIVISOR_REGISTER (0x06C)
|
|
|
|
|
#define I2C_BUS_CLEAR_CONFIG (0x084)
|
|
|
|
|
#define I2C_BUS_CLEAR_STATUS (0x088)
|
|
|
|
|
#define I2C_CONFIG_LOAD (0x08C)
|
2020-11-01 00:58:38 +00:00
|
|
|
#define I2C_INTERFACE_TIMING_0 (0x094)
|
|
|
|
|
#define I2C_INTERFACE_TIMING_1 (0x098)
|
|
|
|
|
#define I2C_HS_INTERFACE_TIMING_0 (0x094)
|
|
|
|
|
#define I2C_HS_INTERFACE_TIMING_1 (0x098)
|
2020-10-31 23:34:06 +00:00
|
|
|
|
|
|
|
|
#define I2C_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (I2C, NAME)
|
|
|
|
|
#define I2C_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (I2C, NAME, VALUE)
|
|
|
|
|
#define I2C_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (I2C, NAME, ENUM)
|
|
|
|
|
#define I2C_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(I2C, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
|
|
|
|
|
|
|
|
|
#define DEFINE_I2C_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (I2C, NAME, __OFFSET__, __WIDTH__)
|
|
|
|
|
#define DEFINE_I2C_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE)
|
|
|
|
|
#define DEFINE_I2C_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
|
|
|
|
#define DEFINE_I2C_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
|
|
|
|
#define DEFINE_I2C_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
|
|
|
|
|
|
|
|
|
/* I2C_CNFG */
|
|
|
|
|
DEFINE_I2C_REG(I2C_CNFG_LENGTH, 1, 3);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_CMD1, 6, WRITE, READ);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_SEND, 9, NOP, GO);
|
2020-11-10 13:02:41 +00:00
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_PACKET_MODE_EN, 10, NOP, GO);
|
2020-10-31 23:34:06 +00:00
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_NEW_MASTER_FSM, 11, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_THREE_BIT_ENUM(I2C_CNFG_DEBOUNCE_CNT, 12, NO_DEBOUNCE, DEBOUNCE_2T, DEBOUNCE_4T, DEBOUNCE_6T, DEBOUNCE_8T, DEBOUNCE_10T, DEBOUNCE_12T, DEBOUNCE_14T);
|
|
|
|
|
|
|
|
|
|
/* I2C_CMD_ADDR0 */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_CMD_ADDR0_7BIT_RW, 0, WRITE, READ);
|
|
|
|
|
DEFINE_I2C_REG(I2C_CMD_ADDR0_7BIT_ADDR, 1, 7);
|
|
|
|
|
|
|
|
|
|
/* I2C_STATUS */
|
|
|
|
|
DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD1_STAT, 0, SL1_XFER_SUCCESSFUL, SL1_NOACK_FOR_BYTE1, SL1_NOACK_FOR_BYTE2, SL1_NOACK_FOR_BYTE3, SL1_NOACK_FOR_BYTE4, SL1_NOACK_FOR_BYTE5, SL1_NOACK_FOR_BYTE6, SL1_NOACK_FOR_BYTE7, SL1_NOACK_FOR_BYTE8, SL1_NOACK_FOR_BYTE9, SL1_NOACK_FOR_BYTE10, RESERVED11, RESERVED12, RESERVED13, RESERVED14, RESERVED15);
|
|
|
|
|
DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD2_STAT, 4, SL2_XFER_SUCCESSFUL, SL2_NOACK_FOR_BYTE1, SL2_NOACK_FOR_BYTE2, SL2_NOACK_FOR_BYTE3, SL2_NOACK_FOR_BYTE4, SL2_NOACK_FOR_BYTE5, SL2_NOACK_FOR_BYTE6, SL2_NOACK_FOR_BYTE7, SL2_NOACK_FOR_BYTE8, SL2_NOACK_FOR_BYTE9, SL2_NOACK_FOR_BYTE10, RESERVED11, RESERVED12, RESERVED13, RESERVED14, RESERVED15);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(I2C_STATUS_BUSY, 8, NOT_BUSY, BUSY);
|
|
|
|
|
|
2020-11-01 00:58:38 +00:00
|
|
|
/* PACKET_TRANSFER_STATUS */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_CONTROLLER_BUSY, 0, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_ARB_LOST, 1, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_DATA, 2, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR, 3, UNSET, SET);
|
|
|
|
|
|
|
|
|
|
/* FIFO_CONTROL */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_RX_FIFO_FLUSH, 0, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_TX_FIFO_FLUSH, 1, UNSET, SET);
|
|
|
|
|
|
|
|
|
|
DEFINE_I2C_REG_TWO_BIT_ENUM(FIFO_CONTROL_FIFO_FLUSH, 0, RX_UNSET_TX_UNSET, RX_SET_TX_UNSET, RX_UNSET_TX_SET, RX_SET_TX_SET);
|
|
|
|
|
|
|
|
|
|
DEFINE_I2C_REG(FIFO_CONTROL_RX_FIFO_TRIG, 2, 3);
|
|
|
|
|
DEFINE_I2C_REG(FIFO_CONTROL_TX_FIFO_TRIG, 5, 3);
|
|
|
|
|
|
2020-11-01 02:14:43 +00:00
|
|
|
/* FIFO_STATUS */
|
|
|
|
|
DEFINE_I2C_REG(FIFO_STATUS_RX_FIFO_FULL_CNT, 0, 4);
|
|
|
|
|
DEFINE_I2C_REG(FIFO_STATUS_TX_FIFO_EMPTY_CNT, 4, 4);
|
|
|
|
|
|
|
|
|
|
/* INTERRUPT_MASK_REGISTER */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_RFIFO_DATA_REQ_INT_EN, 0, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_TFIFO_DATA_REQ_INT_EN, 1, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_ARB_LOST_INT_EN, 2, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_NOACK_INT_EN, 3, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_RFIFO_UNF_INT_EN, 4, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_TFIFO_OVF_INT_EN, 5, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_ALL_PACKETS_XFER_COMPLETE_INT_EN, 6, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_PACKET_XFER_COMPLETE_INT_EN, 7, DISABLE, ENABLE);
|
|
|
|
|
|
2020-10-31 23:34:06 +00:00
|
|
|
/* INTERRUPT_STATUS_REGISTER */
|
2020-11-01 02:14:43 +00:00
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_RFIFO_DATA_REQ, 0, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_TFIFO_DATA_REQ, 1, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_ARB_LOST, 2, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_NOACK, 3, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_RFIFO_UNF, 4, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_TFIFO_OVF, 5, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_ALL_PACKETS_XFER_COMPLETE, 6, UNSET, SET);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_PACKET_XFER_COMPLETE, 7, UNSET, SET);
|
|
|
|
|
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_BUS_CLEAR_DONE, 11, UNSET, SET);
|
2020-10-31 23:34:06 +00:00
|
|
|
|
|
|
|
|
/* CLK_DIVISOR_REGISTER */
|
|
|
|
|
DEFINE_I2C_REG(CLK_DIVISOR_REGISTER_HSMODE, 0, 16);
|
|
|
|
|
DEFINE_I2C_REG(CLK_DIVISOR_REGISTER_STD_FAST_MODE, 16, 16);
|
|
|
|
|
|
|
|
|
|
/* BUS_CLEAR_CONFIG */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_ENABLE, 0, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_TERMINATE, 1, THRESHOLD, IMMEDIATE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_STOP_COND, 2, NO_STOP, STOP);
|
|
|
|
|
DEFINE_I2C_REG(BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD, 16, 8);
|
|
|
|
|
|
2020-11-01 00:58:38 +00:00
|
|
|
/* BUS_CLEAR_STATUS */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_STATUS_BC_STATUS, 0, NOT_CLEARED, CLEARED);
|
|
|
|
|
|
2020-10-31 23:34:06 +00:00
|
|
|
/* CONFIG_LOAD */
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, 0, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_SLV_CONFIG_LOAD, 1, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_TIMEOUT_CONFIG_LOAD, 2, DISABLE, ENABLE);
|
|
|
|
|
DEFINE_I2C_REG(CONFIG_LOAD_RESERVED_BIT_5, 5, 1);
|
2020-11-01 00:58:38 +00:00
|
|
|
|
|
|
|
|
/* INTERFACE_TIMING_0 */
|
|
|
|
|
DEFINE_I2C_REG(INTERFACE_TIMING_0_TLOW, 0, 6);
|
|
|
|
|
DEFINE_I2C_REG(INTERFACE_TIMING_0_THIGH, 8, 6);
|
|
|
|
|
|
|
|
|
|
/* HS_INTERFACE_TIMING_0 */
|
|
|
|
|
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_TLOW, 0, 6);
|
|
|
|
|
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_THIGH, 8, 6);
|
|
|
|
|
|
