2018-02-25 02:34:15 +00:00
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#include "utils.h"
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#include "memory_map.h"
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2018-02-28 18:06:41 +00:00
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#include "arm.h"
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2018-03-03 02:43:46 +00:00
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#include "synchronization.h"
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2018-02-28 12:32:18 +00:00
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/* start.s */
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2018-02-28 06:32:14 +00:00
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void __set_memory_registers(uintptr_t ttbr0, uintptr_t vbar, uint64_t cpuectlr, uint32_t scr,
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uint32_t tcr, uint32_t cptr, uint64_t mair, uint32_t sctlr);
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2018-02-25 19:00:50 +00:00
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uintptr_t get_warmboot_crt0_stack_address(void) {
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2018-02-27 15:10:56 +00:00
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE012_STACK) + 0x800;
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2018-02-25 02:34:15 +00:00
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}
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2018-02-27 01:41:31 +00:00
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2018-03-03 02:43:46 +00:00
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uintptr_t get_warmboot_crt0_stack_address_critsec_enter(void) {
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unsigned int core_id = get_core_id();
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if (core_id) {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGMENT_ID_CORE3_STACK) + 0x1000;
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}
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else {
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return TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x80 * (core_id + 1);
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}
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}
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void warmboot_crt0_critical_section_enter(volatile critical_section_t *critical_section) {
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critical_section_enter(critical_section);
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}
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2018-02-28 12:32:18 +00:00
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void set_memory_registers_enable_mmu(void) {
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static const uintptr_t vbar = TZRAM_GET_SEGMENT_PA(TZRAM_SEGEMENT_ID_SECMON_EVT) + 0x800;
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static const uintptr_t ttbr0 = vbar - 64;
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/*
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- Disable table walk descriptor access prefetch.
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- L2 instruction fetch prefetch distance = 3 (reset value)
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- L2 load/store data prefetch distance = 8 (reset value)
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- Enable the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster
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*/
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static const uint64_t cpuectlr = 0x1B00000040ull;
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/*
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- The next lower level is Aarch64
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- Secure instruction fetch (when the PE is in Secure state, this bit disables instruction fetch from Non-secure memory)
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- External Abort/SError taken to EL3
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- FIQ taken to EL3
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- NS (EL0 and EL1 are nonsecure)
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*/
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static const uint32_t scr = 0x63D;
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/*
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- PA size: 36-bit (64 GB)
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- Granule size: 4KB
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- Shareability attribute for memory associated with translation table walks using TTBR0_EL3: Inner Shareable
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- Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL3: Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
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- Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL3: Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
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- T0SZ = 31 (33-bit address space)
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*/
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static const uint32_t tcr = TCR_EL3_RSVD | TCR_PS(1) | TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA | TCR_T0SZ(33);
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/* Nothing trapped */
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static const uint32_t cptr = 0;
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/*
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- Attribute 0: Normal memory, Inner and Outer Write-Back Read-Allocate Write-Allocate Non-transient
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- Attribute 1: Device-nGnRE memory
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- Other attributes: Device-nGnRnE memory
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*/
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static const uint64_t mair = 0x4FFull;
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/*
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- Cacheability control, for EL3 instruction accesses DISABLED
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(- SP Alignment check bit NOT SET)
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- Cacheability control, for EL3 data accesses DISABLED (normal memory accesses from EL3 are cacheable)
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(- Alignement check bit NOT SET)
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- MMU enabled for EL3 stage 1 address translation
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*/
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static const uint32_t sctlr = 0x30C51835ull;
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__set_memory_registers(ttbr0, vbar, cpuectlr, scr, tcr, cptr, mair, sctlr);
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}
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2018-03-02 04:10:05 +00:00
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void warmboot_init(boot_func_list_t *func_list) {
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2018-03-02 01:19:35 +00:00
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(void)func_list;
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2018-02-27 15:10:56 +00:00
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}
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